IP Library Granted Patent US 8,722,471
Granted Patent B2
US 8,722,471 · App. 13/748,126 · Granted May 13, 2014

Method for forming a via contacting several levels of semiconductor layers

Inventors: Perrine Batude (Grenoble, FR); Yves Morand (Grenoble, FR)
Assignees: STMicroelectronics S.A.; Commissariat à l'Énergie Atomique et aux Énergies Alternatives
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Quick Facts
Patent No.
US 8,722,471
App. No.
13/748,126
Granted
May 13, 2014
Kind
B2
Abstract

A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.

Claims (15)

1. A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method comprising the steps of:

a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge;

b) forming a layer of a protection material on said edge only;

c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and

d) filling the opening with at least one conductive contact material.

2. The method of claim 1 , wherein the protection material is a conductive material.

3. The method of claim 2 , wherein, at step b), the layer of the conductive protection material is formed by electroless deposition.

4. The method of claim 1 , wherein the first and second layers are silicon layers covered with a metal silicide.

5. The method of claim 4 , wherein the metal silicide is based on a metal selected from the group comprising platinum and nickel.

6. The method of claim 1 , wherein:

the thickness of the insulating material separating the first layer from the gates of transistors formed on the second layer ranges between 10 and 500 nm;

the thickness of the first layer ranges between 5 and 150 nm; and

at step b), a layer of the protection material having a thickness ranging between 10 and 50 nm is formed.

7. The method of claim 2 , wherein the conductive protection material is selected from the group comprising platinum and nickel.

8. The method of claim 1 , wherein the conductive contact material is tungsten.

Assignments (2)
CHANGE OF NAME Recorded Jan 21, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066357/0693 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2013
From: MORAND, YVES; BATUDE, PERRINE
To: STMICROELECTRONICS S.A.; COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Reel/Frame 029692/0092 →
Priority Claims (1)
FR 12 50884 · Jan 31, 2012 · national
Continuity (1)
Related Publication 20130196500A1 · Aug 1, 2013