High-K dielectric stack and method of fabricating same
A method for improving the reliability of a high-k dielectric layer or a high-k dielectric stack by forming an amorphous high-k dielectric layer over an insulating layer, doping the amorphous high-k dielectric layer with nitrogen atoms, and subsequently heating the resulting structure at a temperature greater than or equal to the crystallization temperature of the high-k dielectric material, thereby transforming the high-k dielectric material from an amorphous state to a crystalline state, and causing nitrogen atoms to diffuse into the insulating layer.
1. A method of fabricating a semiconductor device, comprising:
forming an insulating layer over a semiconductor substrate;
forming an amorphous high-k dielectric layer over the insulating layer;
doping the amorphous high-k dielectric layer with nitrogen;
heating the amorphous high-K dielectric layer to a temperature that equals or exceeds the crystallization temperature of the amorphous high-K dielectric layer, thereby transforming the amorphous high-K dielectric layer to a crystalline high-k dielectric layer, and causing nitrogen to diffuse from the amorphous high-k dielectric layer into the insulating layer;
forming a conductive electrode layer over the crystalline high-k dielectric layer.
2. The method of claim 1 , wherein the insulating layer comprises silicon oxide.
3. The method of claim 1 , wherein the conductive electrode layer comprises metal or nitrided metal.
4. The method of claim 1 , wherein the conductive electrode layer comprises polysilicon.
5. The method of claim 1 , wherein the amorphous high-k dielectric layer comprises a metal oxide.
6. The method of claim 1 , further comprising forming a silicon nitride/oxynitride layer over the insulating layer and forming the amorphous high-k dielectric layer over the silicon nitride/oxynitride layer.
7. The method of claim 1 , further comprising removing a portion of the crystalline high-k dielectric layer over a first region of the substrate prior to forming the conductive electrode layer.
8. The method of claim 1 , further comprising:
forming a gate dielectric layer over the semiconductor substrate;
forming a floating gate layer over the gate dielectric layer; and
forming the insulating layer over the floating gate layer.
9. The method of claim 1 , further comprising:
forming an electrode structure comprising a metal over the semiconductor substrate; and
forming the insulating layer over the electrode structure.
10. The method of claim 1 , further comprising:
forming a dielectric region over the semiconductor substrate;
forming an electrode structure comprising a metal over the dielectric region; and
forming the insulating layer over the electrode structure.
11. The method of claim 1 , further comprising:
forming a second high-k dielectric layer on the first high-k dielectric layer, wherein the first high-k dielectric layer has a first crystallization temperature and the second high-k dielectric layer has a second crystallization temperature; and
annealing the first and second high-k dielectric layers at an anneal temperature that exceeds the first crystallization temperature.
12. The method of claim 1 , wherein the amorphous high-k dielectric layer is doped with nitrogen by implanting nitrogen ions into the amorphous high-k dielectric layer.
13. The method of claim 1 , wherein the amorphous high-k dielectric layer is doped with nitrogen by plasma treatment in a gas environment containing nitrogen atoms.
14. The method of claim 1 , wherein the amorphous high-k dielectric layer is doped with nitrogen by a bake in a gas environment containing nitrogen atoms.
15. The method of claim 5 , wherein the amorphous high-k dielectric layer comprises alloys of metal oxides.
16. The method of claim 5 , wherein the amorphous high-k dielectric layer comprises alumina.
17. The method of claim 15 , wherein the amorphous high-k dielectric layer comprises alloys of metal oxides with silicates and nitrides.
18. The method of claim 6 , further comprising forming the silicon nitride/oxynitride layer to a thickness of about 10 to 20 Angstroms.
19. The method of claim 11 , wherein the anneal temperature is less than the second crystallization temperature.
20. The method of claim 11 , further comprising:
forming a third high-k dielectric layer on the second high-k dielectric layer; and
doping the third high-k dielectric layer with nitrogen.
21. The method of claim 20 , wherein the first, second and third high-k dielectric layers comprise two or more different materials having two or more crystallization temperatures, the method further comprising annealing the first, second and third high-k dielectric layers at a temperature that equals or exceeds the highest crystallization temperature.
22. The method of claim 20 , wherein the first, second and third high-k dielectric layers comprise two or more different materials having two or more crystallization temperatures, the method further comprising annealing the first, second and third high-k dielectric layers at a temperature that equals or exceeds the crystallization temperature of the first and third high-k dielectric layers.
23. The method of claim 12 , further comprising implanting nitrogen with energies of about 10 eV to 15 keV, and a dosage in the range of E13-E16 cm −2 .
24. The method of claim 13 , wherein the gas environment comprises N 2 , N 2 O, NO or NH3.