Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
1. A method comprising:
forming a first gate structure over a substrate;
forming a dielectric layer over the first gate structure;
removing the first gate structure;
after removing the first gate structure, forming a strained layer over the substrate in an area in which the first gate structure was over the substrate; and
forming a second gate structure over the strained layer.
2. The method of claim 1 , wherein the strained layer adjoins the substrate at an interface.
3. The method of claim 1 , wherein the strained layer has a distal zone a distance away from the substrate, wherein the strained layer and substrate are characterized at least in part by an impurity gradient describing an impurity concentration as a function of location, the impurity concentration having a value substantially equal to zero in the distal zone.
4. The method of claim 3 , wherein the impurity is an n-type dopant or a p-type dopant.
5. The method of claim 3 , wherein the impurity is silicon or germanium.
6. A method comprising:
doping a substrate with an impurity to form a channel region;
forming a strained channel layer over the channel region, the strained channel layer having a distal zone away from the substrate; and
forming a gate structure over the strained channel layer, wherein the substrate has a greatest concentration of the impurity in a location proximate an interface of the substrate and the strained channel layer, the substrate having a first decreasing concentration of the impurity in a first direction away from the location, and the strained channel layer having a second decreasing concentration of the impurity in a second direction away from the location, the distal zone having a substantially zero concentration of the impurity in the distal zone.
7. The method of claim 6 , wherein the impurity is an n-type dopant or a p-type dopant.
8. The method of claim 6 , wherein the impurity is silicon or germanium.
9. The method of claim 6 , wherein the substrate comprises a crystalline material that is lattice mismatched to the strained channel layer, the crystalline material adjoining the strained channel layer.
10. The method of claim 1 , wherein the strained layer comprises a first concentration of an impurity in a first portion adjacent an interface with the substrate and a second concentration of the impurity in a second portion distal from the interface, the first concentration being greater than the second concentration.
11. The method of claim 10 , wherein the strained layer comprises a third concentration in a third portion disposed between the first portion and the second portion, the third concentration being greater than the second concentration.
12. The method of claim 10 , wherein the second concentration is substantially equal to zero.
13. The method of claim 6 , wherein the strained channel layer has a compressive strain.
14. The method of claim 6 , wherein the strained channel layer has a tensile strain.
15. A method comprising:
forming a dummy gate structure over an area of a substrate;
forming a dielectric layer over the dummy gate structure;
exposing the dummy gate structure through the dielectric layer;
removing the dummy gate structure;
after removing the dummy gate structure, forming a strained channel layer over the area of the substrate; and
forming a functional gate structure over the strained channel layer.
16. The method of claim 15 , wherein the forming the strained channel layer comprises introducing a dopant in the strained channel layer, the dopant having a decreasing concentration from near the substrate to a distal zone distal from the substrate.
17. The method of claim 15 , wherein the strained channel layer is strained by a strain-inducing underlying material.
18. The method of claim 15 , wherein the strained channel layer comprises a strain induced by an overlying layer.
19. The method of claim 15 , wherein the strained channel layer has a distal zone a distance away from the substrate, wherein the strained channel layer and substrate are characterized at least in part by an impurity gradient describing an impurity concentration as a function of location, the impurity concentration having a value substantially equal to zero in the distal zone.
20. The method of claim 15 , wherein the exposing the dummy gate structure includes planarizing the dielectric layer.