Interfacial layer for DRAM capacitor
View Patent ↗A method for reducing leakage current in DRAM capacitor stacks by introducing dielectric interface layers between the electrodes and the bulk dielectric material. The dielectric interface layers are typically amorphous dielectric materials with a k value between about 10 and about 30 and are less than about 1.5 nm in thickness. Advantageously, the thickness of each of the dielectric interface layers is less than 1.0 nm. In some cases, only a single dielectric interface layer is used between the bulk dielectric material and the second electrode.
1. A method for forming a capacitor stack, the method comprising:
forming a first electrode layer on a substrate;
forming a first interface dielectric layer on the first electrode layer,
wherein the k value of the first interface dielectric layer is between about 10 and about 30,
wherein the first interface dielectric layer comprises one of La 2 O 3 , Lu 2 O 3 , Er 2 O 3 , MgO, Ga 2 O 3 , or combinations thereof;
forming a bulk dielectric layer on the first interface dielectric layer,
wherein the k value of the bulk dielectric layer is at least about 40;
forming a second interface dielectric layer on the bulk dielectric layer
wherein the k value of the second interface dielectric layer is between about 10 and about 30,
wherein the first interface dielectric layer and the second interface dielectric layer directly interface the bulk dielectric layer and increase a barrier height between the first electrode layer and the bulk dielectric layer and a barrier height between the second electrode layer and the bulk dielectric layer; and
forming a second electrode on the second interface dielectric layer.
2. The method of claim 1 , wherein a thickness of each of the first and second interface dielectric layers is less than about 1.5 nm.
3. The method of claim 2 , wherein the thickness of each of the first and second interface dielectric layers is less than about 1.0 nm.
4. The method of claim 1 , wherein each of the first interface dielectric layer and the second interface dielectric layer is amorphous.
5. The method of claim 1 , wherein the second interface dielectric layer comprises one of La 2 O 3 , Si X N Y , Lu 2 O 3 , Er 2 O 3 , MgO, Ga 2 O 3 , or combinations thereof.
6. The method of claim 1 , wherein the bulk dielectric layer comprises TiO 2 and a dopant, wherein the dopant comprises one or more of Al, Ge, Ga, Sr, Y, La, Zr, Hf, Sc, Nd, Ce, In, Sn, Er, Gd, Mg, Mn, Lu, Pr, Co, S, Se, Te, C, F, Cl, Br, I, P, As, Sb, or Bi.
7. A method for forming a capacitor stack, the method comprising:
forming a first electrode layer on a substrate;
forming a bulk dielectric layer on the first electrode layer,
wherein the k value of the bulk dielectric layer is at least about 40;
forming a second interface dielectric layer on the bulk dielectric layer
wherein the k value of the second interface dielectric layer is between about 10 and about 30,
wherein the second interface dielectric layer comprises one of La 2 O 3 , Lu 2 O 3 , Er 2 O 3 , MgO, Ga 2 O 3 , or combinations thereof;
wherein the second interface dielectric layer directly interfaces the bulk dielectric layer and increases a barrier height between the second electrode layer and the bulk dielectric layer; and
forming a second electrode on the second interface dielectric layer.
8. The method of claim 7 , wherein a thickness of the second interface dielectric layer is less than about 1.5 nm.
9. The method of claim 8 , wherein the thickness of the second interface dielectric layer is less than about 1.0 nm.
10. The method of claim 7 , wherein the second interface dielectric layer is amorphous.
11. The method of claim 7 , wherein the bulk dielectric layer comprises TiO 2 and a dopant, and wherein the dopant comprises one or more of Al, Ge, Ga, Sr, Y, La, Zr, Hf, Sc, Nd, Ce, In, Sn, Er, Gd, Mg, Mn, Lu, Pr, Co, S, Se, Te, C, F, Cl, Br, I, P, As, Sb, or Bi.
12. A method for forming a capacitor stack, the method comprising:
forming a first electrode layer on a substrate;
forming a first interface dielectric layer on the first electrode layer
wherein the k value of the first interface dielectric layer is between about 10 and about 30,
wherein the first interface dielectric layer comprises one of La 2 O 3 , Lu 2 O 3 , Er 2 O 3 , MgO, Ga 2 O 3 , or combinations thereof;
forming a bulk dielectric layer on the first interface dielectric layer,
wherein the k value of the bulk dielectric layer is at least about 40;
wherein the first interface dielectric layer directly interfaces the bulk dielectric layer and increases a barrier height between the first electrode layer and the bulk dielectric layer; and
forming a second electrode on the bulk dielectric layer.
13. The method of claim 12 , wherein the bulk dielectric layer comprises TiO 2 and a dopant, and wherein the dopant comprises one or more of Al, Ge, Ga, Sr, Y, La, Zr, Hf, Sc, Nd, Ce, In, Sn, Er, Gd, Mg, Mn, Lu, Pr, Co, S, Se, Te, C, F, Cl, Br, I, P, As, Sb, or Bi.
14. The method of claim 1 , wherein the bulk dielectric layer is a nanolaminate.
15. The method of claim 1 , wherein the bulk dielectric comprises titanium oxide doped with aluminum.
16. The method of claim 1 , wherein, prior to forming the second interface dielectric layer, the capacitor stack comprising the substrate, the first electrode layer, the first interface dielectric layer, and the bulk dielectric layer is annealed.
17. The method of claim 1 , wherein the first interface dielectric layer and the second interface dielectric layer have different composition.
18. The method of claim 1 , wherein the first electrode layer comprises a metal oxide.
19. The method of claim 1 , wherein the first electrode layer comprises one of molybdenum oxide, tungsten oxide, ruthenium oxide, iron oxide, iridium oxide, chromium oxide, manganese oxide, tin oxide, cobalt oxide, or nickel oxide.
20. The method of claim 1 , wherein the first interface dielectric layer comprises a combination of two or more of La 2 O 3 , Lu 2 O 3 , Er 2 O 3 , MgO, or Ga 2 O 3 .