FinFET device and method of manufacturing same
View Patent ↗A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.
1. A semiconductor device comprising:
a substrate including a fin structure disposed over the substrate, the fin structure including one or more fins;
an insulation material disposed on the substrate and formed in a region between each of the one or more fins;
a dielectric layer traversing each of the one or more fins and formed on the insulation material in the region between each of the one or more fins;
a work function metal traversing each of the one or more fins and formed on the dielectric layer in the region between each of the one or more fins;
a strained material disposed on the work function metal in the region between each of the one or more fins; and
a signal metal traversing each of the one or more fins and formed on the work function metal and on the strained material.
2. The semiconductor device of claim 1 wherein the strained material has a coefficient of thermal expansion (CTE) that is different than a CTE of the work function metal and a CTE of the signal metal, and
wherein the signal metal separates source and drain regions of the semiconductor device, the source and drain regions defining a channel region, for each of the one or more fins, therebetween.
3. The semiconductor device of claim 2 wherein the strained material induces a compressive stress in a current flow direction of the channel region, for each of the one or more fins.
4. The semiconductor device of claim 2 wherein the strained material induces a tensile stress in a current flow direction of the channel region, for each of the one or more fins.
5. The semiconductor device of claim 1 wherein the semiconductor device is one of a P-type metal-oxide-semiconductor (PMOS) fin-like field effect transistor (FinFET) device or a N-type metal-oxide-semiconductor (NMOS) FinFET device, and wherein the semiconductor device is included in an integrated circuit device.
6. The semiconductor device of claim 1 wherein the strained material is selected from the group consisting of a dielectric material and a metal material.
7. The semiconductor device of claim 1 wherein the strained material includes titanium silicide (TiSi) and the work function metal includes titanium nitride (TiN).
8. The semiconductor device of claim 1 wherein the strained material includes polyimide (PI) and the work function metal includes titanium aluminide (TiAl).
9. A semiconductor device comprising:
a substrate;
a fin structure including one or more fins disposed over the substrate;
a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins;
a work function metal disposed on the dielectric layer and traversing each of the one or more fins;
a strained material disposed on the work function metal and interposed between each of the one or more fins; and
a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.
10. The semiconductor device of claim 9 wherein the signal metal separates source and drain regions of the semiconductor device, the source and drain regions defining a channel region, for each of the one or more fins, therebetween,
wherein the strained material induces a compressive stress in a current flow direction of the channel region of at least one fin of the one or more fins of the fin structure, and
wherein the strained material has a coefficient of thermal expansion (CTE) that is less than a CTE of the work function metal and different than a CTE of the signal metal.
11. The semiconductor device of claim 10 wherein the semiconductor device is a P-type metal-oxide-semiconductor (PMOS) fin-like field effect transistor (FinFET) device.
12. The semiconductor device of claim 9 wherein the signal metal separates source and drain regions of the semiconductor device, the source and drain regions defining a channel region, for each of the one or more fins, therebetween,
wherein the strained material induces a tensile stress in a current flow direction of the channel region of at least one fin of the one or more fins of the fin structure, and
wherein the strained material has a coefficient of thermal expansion (CTE) that is greater than a CTE of the work function metal and different than a CTE of the signal metal.
13. The semiconductor device of claim 12 wherein the semiconductor device is a N-type metal-oxide-semiconductor (NMOS) fin-like field effect transistor (FinFET) device.