Memory device and method for manufacturing the same
According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a first memory region; and a second memory region. The transistor controls a conduction of each of a current flowing between the first and the second signal lines and an opposite current. The first memory region has a first magnetic tunnel junction element. A magnetization direction thereof becomes parallel when a current flows in one direction, and the magnetization direction becomes antiparallel when a current in another direction. The second memory region has a second magnetic tunnel junction element. A magnetization direction thereof becomes parallel when a current flows in one direction, and becomes antiparallel when a current flows in another first direction.
1. A memory device, comprising:
a first signal line;
a second signal line;
a transistor configured to control a conduction of each of a current in a first direction flowing between the first signal line and the second signal line and a current in a second direction opposite to the first direction;
a first memory region having a first magnetic tunnel junction element which is connected between the first signal line and one end of the transistor, a magnetization direction of which becomes parallel when a current not less than a first parallel threshold value flows in the first direction, and the magnetization direction of which becomes antiparallel when a current not less than a first antiparallel threshold value flows in the second direction; and
a second memory region having a second magnetic tunnel junction element which is connected between the second signal line and other end of the transistor, a magnetization direction of which becomes parallel when a current not less than a second parallel threshold value larger than the first parallel threshold value flows in the second direction, and the magnetization direction of which becomes antiparallel when a current not less than a second antiparallel threshold value larger than the first antiparallel threshold value flows in the first direction.
2. The memory device according to claim 1 , wherein:
the first magnetic tunnel junction element includes a first stacked body, wherein a first magnetization free layer, a first tunnel barrier layer, and a first magnetization fixed layer are stacked in this order;
the second magnetic tunnel junction element includes a second stacked body, wherein a second magnetization free layer, a second tunnel barrier layer, and a second magnetization fixed layer are stacked in this order; and
along the first direction, a stacking order of the first stacked body and a stacking order of the second stacked body become opposite to each other.
3. The memory device according to claim 2 , wherein a volume of the first magnetization free layer is smaller than a volume of the second magnetization free layer.
4. The memory device according to claim 2 , wherein
the first magnetization free layer and the second magnetization free layer are provided in a same thickness on a same plane;
the first tunnel barrier layer and the second tunnel barrier layer are provided in a same thickness on a same plane; and
the first magnetization fixed layer and the second magnetization fixed layer are provided in a same thickness on a same plane.
5. The memory device according to claim 1 , wherein the first memory region includes a third magnetic tunnel junction element which is provided between the first signal line and the first magnetic tunnel junction element, a magnetization direction of which becomes parallel when a current not less than a third parallel threshold value smaller than the first parallel threshold value flows in the first direction, and the magnetization direction of which becomes antiparallel when a current not less than a third antiparallel threshold value smaller than the first antiparallel threshold value flows in the second direction.
6. The memory device according to claim 2 , wherein:
the first memory region includes a third magnetic tunnel junction element which is provided between the first signal line and the first magnetic tunnel junction element, a magnetization direction of which becomes parallel when a current not less than a third parallel threshold value smaller than the first parallel threshold value flows in the first direction, and the magnetization direction of which becomes antiparallel when a current not less than a third antiparallel threshold value smaller than the first antiparallel threshold value flows in the second direction;
the third magnetic tunnel junction element includes a third stacked body, wherein a third magnetization free layer, a third tunnel barrier layer, and a third magnetization fixed layer are stacked in this order; and
along the first direction, a stacking order of the first stacked body is the same as a stacking order of the third stacked body.
7. The memory device according to claim 1 , wherein the second memory region includes a fourth magnetic tunnel junction element which is provided between the second signal line and the second magnetic tunnel junction element, a magnetization direction of which becomes parallel when a current not less than a fourth parallel threshold value smaller than the second parallel threshold value flows in the second direction, and the magnetization direction of which becomes antiparallel when a current not less than a fourth antiparallel threshold value smaller than the second antiparallel threshold value flows in the first direction.
8. The memory device according to claim 2 , wherein:
the second memory region includes a fourth magnetic tunnel junction element which is provided between the second signal line and the second magnetic tunnel junction element, a magnetization direction of which becomes parallel when a current not less than a fourth parallel threshold value smaller than the second parallel threshold value flows in the second direction, and the magnetization direction of which becomes antiparallel when a current not less than a fourth antiparallel threshold value smaller than the second antiparallel threshold value flows in the first direction;
the fourth magnetic tunnel junction element includes a fourth stacked body, wherein a fourth magnetization free layer, a fourth tunnel barrier layer, and a fourth magnetization fixed layer are stacked in this order; and
along the first direction, a stacking order of the second stacked body is the same as a stacking order of the fourth stacked body.
9. The memory device according to claim 6 , wherein:
the second memory region includes a fourth magnetic tunnel junction element which is provided between the second signal line and the second magnetic tunnel junction element, a magnetization direction of which becomes parallel when a current not less than a fourth parallel threshold value smaller than the second parallel threshold value flows in the second direction, and the magnetization direction of which becomes antiparallel when a current not less than a fourth antiparallel threshold value smaller than the second antiparallel threshold value flows in the first direction;
the fourth magnetic tunnel junction element includes a fourth stacked body, wherein a fourth magnetization free layer, a fourth tunnel barrier layer, and a fourth magnetization fixed layer are stacked in this order; and
along the first direction, a stacking order of the second stacked body is the same as a stacking order of the fourth stacked body.
10. The memory device according to claim 1 , wherein a resistance value when a magnetization direction of the first magnetic tunnel junction element is antiparallel is larger than a resistance value when a magnetization direction of the second magnetic tunnel junction element is antiparallel.
11. The memory device according to claim 1 , further comprising a plurality of the first memory regions and a plurality of the second memory regions, wherein:
the plurality of first memory regions are disposed in a row direction and in a column direction at a same pitch, respectively;
the plurality of second memory regions are disposed in the row direction and in the column direction at the same pitch, respectively; and
the plurality of first memory regions and the plurality of second memory regions are disposed with a half pitch offset to each other in the row direction and in the column direction.
12. The memory device according to claim 11 , further comprising:
a plurality of the transistors provided at a first pitch in each of the row direction and the column direction;
a plurality of the first signal lines and a plurality of the second signal lines extending in one of the row direction and the column direction and alternately disposed one by one at a second pitch half the first pitch; and
a plurality of control lines extending in the other of the row direction and the column direction and arranged at the first pitch, wherein
the first memory region and the second memory region are formed in each of the plurality of transistors.
13. The memory device according to claim 1 , wherein a set of the one first memory region and the one second memory region stores at least 2 bits of information.