Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device comprising:

a plurality of memory units each having a memory string which comprises memory transistors and select transistors;

a plurality of bit lines, one end of each of the memory units being connected to one of the plurality of bit lines;

a plurality of word lines connected to the memory transistors;

a plurality of control gate lines connected to the select transistors; and

a control circuit configured to control: an erase operation to erase data of the memory transistors; a correction write operation moving an erase threshold level of the memory transistors to a positive threshold level after the erase operation; and a correction write verify operation determining whether or not a threshold level of a result of the correction write operation reaches a first value,

in the correction write operation, the control circuit executing the correction write operation with respect to a group of the plurality of memory units connected to a common one of the bit lines and sequentially executing the correction write verify operation with respect to the group of the plurality of memory units in which the correction write operation is executed.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein

the memory string comprises:

a first semiconductor layer comprising a columnar portion extending in a vertical direction with respect to a substrate and functioning as bodies of the memory transistors;

a charge accumulation layer surrounding a side surface of the columnar portion and configured to enable to accumulate charges; and

a plurality of first conductive layers surrounding the side surface of the columnar portion through the charge accumulation layer and functioning as gates of the memory transistors,

each of the select transistors comprises:

a second semiconductor layer extending in a vertical direction with respect to a substrate and functioning as one of bodies of the select transistors;

a gate insulating layer surrounding a side surface of the second semiconductor layer; and

a second conductive layer surrounding the side surface of the second semiconductor layer through the gate insulating layer and functioning as one of gates of the select transistors.

3. The nonvolatile semiconductor memory device according to claim 1 , wherein

the control circuit inhibits the correction write operation with respect to a memory transistor after a determination that a threshold level of a result of the correction write operation of the memory transistor reaches the first value by the correction write verify operation.

4. The nonvolatile semiconductor memory device according to claim 1 , wherein

the control circuit comprises a plurality of latch circuits, and

the plurality of latch circuits each stores information regarding whether or not a threshold level of a result of the correction write operation reaches the first value.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein

the memory transistors are configured to enable to store multivalued data.

6. The nonvolatile semiconductor memory device according to claim 1 , wherein

the control circuit comprises three latch circuits,

the three latch circuits each stores information regarding whether or not a threshold level of a result of the correction write operation reaches the first value, and

the memory transistors are configured to enable to store data of 2 bits.

7. The nonvolatile semiconductor memory device according to claim 1 , wherein

the control circuit executes the erase operation with respect to the group of the plurality of the memory units.

8. The nonvolatile semiconductor memory device according to claim 1 , wherein

the control circuit applies a first voltage to gates of the memory transistors to execute the correction write operation and then applies a second voltage to the gates of the memory transistors to execute the correction write operation again, and

the second voltage is larger than the first voltage.

9. The nonvolatile semiconductor memory device according to claim 1 , wherein

the control circuit sets a memory unit after a determination that a threshold level of a result of the correction write operation of the memory unit reaches the first value in the correction write verify operation to a write inhibit memory unit, and

the control circuit raises a voltage of a body of a memory transistor in the write inhibit memory unit before executing the correction write operation and thereby inhibits the correction write operation with respect to the write inhibit memory unit.

10. The nonvolatile semiconductor memory device according to claim 9 , wherein

the control circuit discharges voltages of bodies of the memory transistors in the write inhibit memory unit and other memory units to a ground voltage and then charges the voltages of the bodies of the memory transistors in the write inhibit memory unit from the bit lines.

11. A nonvolatile semiconductor memory device comprising:

a plurality of memory units having a plurality of memory strings which comprises memory transistors and select transistors;

a plurality of bit lines, one end of each of the memory units being connected to one of the plurality of bit lines;

a plurality of word lines connected to the memory transistors;

a plurality of control gate lines connected to the select transistors; and

a control circuit configured to control: an erase operation to erase data of the memory transistors; a correction write operation moving an erase threshold level of the memory transistors to a positive threshold level after the erase operation; and a correction write verify operation determining whether or not a threshold level of a result of the correction write operation reaches a first value,

the memory string comprising:

a first semiconductor layer comprising a columnar portion extending in a vertical direction with respect to a substrate and functions as bodies of the memory transistors;

a charge accumulation layer surrounding a side surface of the columnar portion and configured to enable to accumulate charges; and

a plurality of first conductive layers surrounding the side surface of the columnar portion through the charge accumulation layer and function as gates of the memory transistors, and

in the correction write operation, the control circuit executing the correction write operation with respect to a group of the plurality of memory units connected to a common one of the bit lines.

12. The nonvolatile semiconductor memory device according to claim 11 , wherein

the memory transistors are configured to enable to store multivalued data.

13. The nonvolatile semiconductor memory device according to claim 11 , wherein

the control circuit executes the erase operation with respect to the group of the plurality of the memory units.

14. The nonvolatile semiconductor memory device according to claim 11 , wherein

the control circuit applies a first voltage to the gates of the memory transistors to execute the correction write operation and then applies a second voltage to the gates of the memory transistors to execute the correction write operation again, and

the second voltage is larger than the first voltage.

15. The nonvolatile semiconductor memory device according to claim 11 , wherein

the control circuit sets a predetermined memory unit to a write inhibit memory unit, and the control circuit raises a voltage of a body of a memory transistor in the write inhibit memory unit before executing the correction write operation and thereby inhibits the correction write operation with respect to the write inhibit memory unit.

16. The nonvolatile semiconductor memory device according to claim 15 , wherein

the control circuit discharges voltages of bodies of the memory transistors in the write inhibit memory unit and other memory units to a ground voltage and then charges the voltages of the bodies of the memory transistors in the write inhibit memory unit from the bit lines.

17. A nonvolatile semiconductor memory device comprising:

a plurality of memory units each having a plurality of memory strings which comprises memory transistors and select transistors;

a plurality of bit lines extending in a first direction, one end of each of the memory units being connected to one of the plurality of bit lines;

a plurality of word lines connected to the memory transistors;

a plurality of control gate lines connected to the select transistors and extending in a second direction perpendicular to the first direction; and

a control circuit configured to control: an erase operation to erase data of the memory transistors; a correction write operation moving an erase threshold level of the memory transistors to a positive threshold level after the erase operation; and a correction write verify operation determining whether or not a threshold level of a result of the correction write operation reaches a first value,

in the correction write operation, the control circuit executing the correction write operation with respect to a group of the plurality of the memory units connected to a common one of the bit lines and sequentially executing the correction write verify operation with respect to the plurality of memory units in which the correction write operation is executed, and the correction write verify operation being executed for each of the memory units connected to a common control gate line.

18. The nonvolatile semiconductor memory device according to claim 17 , wherein

after all the memory units connected to the common control gate line are determined as pass by the correction write verify operation, the correction write verify operation applied to the memory units connected to the common control gate line is omitted.