High gate density devices and methods
A semiconductor device with an isolation feature is disclosed. The semiconductor device includes a plurality of gate structures disposed on a semiconductor substrate, a plurality of gate sidewall spacers of a dielectric material formed on respective sidewalls of the plurality of gate structures, an interlayer dielectric (ILD) disposed on the semiconductor substrate and the gate structures, an isolation feature embedded in the semiconductor substrate and extended to the ILD and a sidewall spacer of the dielectric material disposed on sidewalls of extended portion of the isolation feature.
1. A semiconductor device, comprising:
a plurality of gate structures disposed on a semiconductor substrate;
a plurality of gate sidewall spacers of a dielectric material formed on respective sidewalls of the plurality of gate structures;
an interlayer dielectric (ILD) disposed on a top surface the semiconductor substrate and the gate structures, wherein the ILD has a topmost surface facing away from the top surface of the substrate;
an isolation feature embedded in the semiconductor substrate and extended to the ILD, wherein the isolation feature has a topmost surface facing away from the top surface of the substrate; and
a sidewall spacer of the dielectric material disposed on sidewalls of extended portion of the isolation feature, and
wherein the topmost surface of the ILD is substantially coplanar with the topmost surface of the isolation feature.
2. The semiconductor device of claim 1 , further comprising epitaxial growth regions near the isolation feature and near the gate structures.
3. The semiconductor device of claim 2 , wherein the epitaxial growth regions have a uniform shape to each other.
4. The semiconductor device of claim 2 , wherein the epitaxial growth regions have uniform crystal facets to each other.
5. The semiconductor device of claim 1 , wherein the epitaxial growth regions includes silicon germanium.
6. The semiconductor device of claim 1 , wherein the isolation feature comprises a sidewall spacer on an upper portion of the isolation feature.
7. The semiconductor device of claim 6 , wherein the profile of the isolation feature is aligned to edges of the sidewall spacer.
8. The semiconductor device of claim 1 , wherein the sidewall spacer comprises silicon nitride.
9. The semiconductor device of claim 1 , wherein the isolation feature comprises one or more dielectric materials.
10. The semiconductor device of claim 9 , wherein the dielectric materials of the isolation feature includes a silicon oxide liner.
11. The semiconductor device of claim 10 , wherein the dielectric materials of the isolation feature includes silicon oxide on top of the silicon oxide liner.
12. The semiconductor device of claim 1 , further comprising a first sidewall spacer physically contacting a first sidewall of the isolation feature and a second sidewall spacer physically contacting a second sidewall of the isolation feature, wherein the first sidewall of the isolation feature opposes the second sidewall of the isolation feature.
13. The semiconductor device of claim 1 , wherein the first and second sidewall spacers physically contact the top surface of the semiconductor substrate.
14. The semiconductor device of claim 1 , wherein the first sidewall spacer has a topmost surface facing away from the semiconductor substrate, and
wherein the topmost surface of the first sidewall spacer is substantially coplanar with the topmost surface of the ILD.
15. The semiconductor device of claim 1 , wherein the topmost surface of the isolation structure is free of the ILD.
16. A semiconductor device, comprising:
a silicon substrate;
two high-k/metal gate (HK/MG) features disposed on the substrate;
a plurality gate spacers of dielectric material formed on respectively sidewalls of the HK/MG features;
a plurality of epitaxial growth silicon germanium regions formed between the two HK/MG features, wherein the epitaxial growth regions have a uniform shape and uniform crystal facets to each other; and
an ILD disposed on a top surface of the semiconductor substrate and HK/MG features, wherein the ILD has a topmost surface facing away from the top surface of the substrate;
an isolation feature embedded in the semiconductor substrate and extended to the ILD such that a topmost surface of the isolation feature facing away from the top surface of the substrate is substantially coplanar with topmost surface of the ILD; and
a sidewall spacer of dielectric material disposed on sidewalls of extended portion of the isolation features.
17. The semiconductor device of claim 16 , further comprising a first sidewall spacer physically contacting a first sidewall of the isolation feature and a second sidewall spacer physically contacting a second sidewall of the isolation feature, wherein the first sidewall of the isolation feature opposes the second sidewall of the isolation feature.
18. The semiconductor device of claim 17 , wherein the first sidewall spacer physically contacts the top surface of the semiconductor substrate.
19. The semiconductor device of claim 17 , wherein the first sidewall spacer has a topmost surface facing away from the semiconductor substrate, and
wherein the topmost surface of the first sidewall spacer is substantially coplanar with the topmost surface of the ILD.
20. The semiconductor device of claim 17 , wherein the isolation feature is positioned between the two HK/MG features disposed on the substrate.