IP Library › Granted Patent US 8,736,337
Granted Patent B2
US 8,736,337 · App. 13/333,448 · Granted May 27, 2014

Semiconductor device, with high-resolution and wide-range adjustable clock

Inventors: Kosuke Yayama (Kanagawa, JP); Takashi Nakamura (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,736,337
App. No.
13/333,448
Granted
May 27, 2014
Kind
B2
Abstract

A clock signal capable of changing the frequency in a wide range and with high resolution is generated. An operational amplifier AMP 1 is subject to feedback control so that the voltage of a positive input part equals that of a negative input part. The voltage of a circuit node fbck equals a reference voltage VREFI. A decoder DEC decodes control signals CNT 7 and CNT 6 and turns on one of transistors T 2 to T 5 . This configuration provides feedback control so that the voltage of the circuit node fbck equals the reference voltage VREFI. This significantly reduces the on-resistances of the transistors T 2 to T 5 and prevents the degradation of the frequency accuracy.

Claims (32)

1. A semiconductor device comprising:

a clock oscillation circuit which comprises a voltage current conversion circuit, a frequency-voltage conversion circuit, and an oscillation circuit outputting a clock signal,

wherein the voltage-current conversion circuit includes

a transistor supplying a reference current;

an operational amplifier having a positive input part, a negative input part, and an output part;

a first resistor-switching section connected between a drain of the transistor and a first node;

a second resistor-switching section connected between the first node; and

a ground voltage line to which a ground voltage is supplied,

wherein the first resistor-switching section has a first resistor section of which a first end is connected to the first node and a first path-switching section including a first and a second switch connected to the drain of the transistor,

wherein the first resistor section includes a first resistor and a first plurality of additional resistors connected in series,

wherein the first path-switching section determines whether to supply the reference current to the first resistor and the second resistor-switching section via the first switch or to supply the reference current to the second resistor-switching section via the second switch without feeding the reference current to the first resistor, using a control signal,

wherein the negative input part of the operational amplifier is supplied a reference voltage, the positive input part of the operational amplifier is connected to the second end of the first resistor section, and the output part of the operational amplifier is connected to a gate of the transistor, and

wherein the frequency-voltage conversion circuit outputs an output voltage to the oscillation circuit according to an output current outputted from the voltage-current conversion circuit and a frequency of the clock signal.

2. The semiconductor device according to claim 1 , wherein

each of the first resistor section and the second resistor section includes a metal wiring resistor.

3. The semiconductor device according to claim 2 , wherein

the first resistor section is in an upper layer of the first path-switching section and the second resistor section is in an upper layer of the second path-switching section.

4. The semiconductor device according to claim 1 , wherein

each of the first resistor section and the second resistor section includes a polysilicon resistor.

5. The semiconductor device according to claim 1 ,

wherein the second resistor-switching section has a second resistor section which includes a second resistor and in which a second plurality of additional resistors is connected in series, and a second path-switching section which includes a third switch controlled by the control signal, and

wherein the third switch is connected in parallel to the second resistor.

6. The semiconductor device according to claim 5 , wherein

the first switch and the second switch are P-channel MOS transistors and the third switch is an N-channel MOS transistor.

7. The semiconductor device according to claim 5 , wherein

the first switch and the second switch are nearer to the first resistor section than to the second resistor section, the third switch is nearer to the second resistor section than to the first resistor section, and the first switch, the second switch, and the third switch are separated from each other.

8. The semiconductor device according to claim 5 , wherein

a resistance of the first resistor is larger than that of the resistors constituting the second resistor section.

9. The semiconductor device according to claim 8 ,

wherein the second plurality of additional resistors connected in series constituting the second resistor section has a resistance of twice sequentially from the resistor connected to the reference voltage line, respectively, and

wherein at least one of the resistors constituting the first resistor section has twice a resistance of a largest resistor among the resistors constituting the second resistor section.

10. The semiconductor device of claim 1 , wherein the oscillation circuit includes an integration circuit and a voltage-controlled oscillation circuit.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2011
From: YAYAMA, KOSUKE; NAKAMURA, TAKASHI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 027432/0628 →
Priority Claims (1)
JP 2010-291630 · Dec 28, 2010 · national
Continuity (1)
Related Publication 20120161868A1 · Jun 28, 2012