Method of forming process for variable resistive element and non-volatile semiconductor memory device
A method of a forming process for a variable resistive element, which is performed in short time comparable to the pulse forming and a writing current in a switching action is the same level as that of the DC forming, is provided. In the forming process, a variable resistive element is changed by voltage pulse application from an initial high resistance state just after produced to a variable resistance state where the switching action is performed. The forming process includes a first step of applying a first pulse having a voltage amplitude lower than a threshold voltage at which the resistance of the variable resistive element is lowered, to between both electrodes of the variable resistive element, and a second step of applying a second pulse having a voltage amplitude having the same polarity as the first pulse and not lower than the threshold voltage, thereto after the first step.
1. A method of a forming process for a variable resistive element provided with a variable resistor formed of a metal oxide, and a first electrode and a second electrode sandwiching the variable resistor, wherein
a resistance state between the first and second electrodes in the variable resistive element is lowered by the forming process, so that the variable resistive element is changed from an initial high resistance state to a variable resistance state in which the resistance state is switched between two or more different resistance states by an applied voltage,
the variable resistive element in the variable resistance state is allowed to hold the resistance state in a non-volatile manner, and
the forming process comprises:
a first step of applying a first pulse having a voltage amplitude set to be lower than a threshold voltage at which the resistance of the variable resistive element is lowered, to between the first and second electrodes of the variable resistive element; and
a second step of applying a second pulse having a voltage amplitude having the same polarity as that of the first pulse and set to be not lower than the threshold voltage, to between the first and second electrodes of the variable resistive element after the first step.
2. The method of the forming process according to claim 1 , wherein
application of the first pulse in the first step, and application of the second pulse in the second step are continuously performed by connecting an end of the first pulse to a start of the second pulse.
3. The method of the forming process according to claim 1 , wherein
the first pulse has a gradually increasing voltage amplitude.
4. The method of the forming process according to claim 1 , wherein
the variable resistor comprises a metal oxide showing n-type conductivity.
5. The method of the forming process according to claim 4 , wherein
the variable resistor comprises a metal oxide selected from Ti, Ta, Hf, and Zr.
6. The method of the forming process according to claim 1 , wherein
a work function of the first electrode is 4.5 eV or less, and a work function of the second electrode is 4.5 eV or more.
7. A non-volatile semiconductor memory device having a memory cell, the memory cell including a variable resistive element and a selection transistor, wherein
the variable resistive element is provided with a variable resistor comprising a metal oxide, and a first electrode and a second electrode sandwiching the variable resistor,
the selection transistor is provided with a control terminal and a pair of input and output terminals,
a resistance state between the first and second electrodes of the variable resistive element is lowered by a forming process, so that the variable resistive element is changed from an initial high resistance state before the forming process to a variable resistance state, the resistance state is switched between two or more resistance states by an electric stress applied to between the first and second electrodes of the variable resistive element in the variable resistance state, and one switched resistance state is used for storing information,
one of the first electrode and the second electrode of the variable resistive element is connected to one end of the pair of the input and output terminals of the selection transistor to constitute the memory cell, and the device comprises:
a memory cell array provided by arranging the memory cells in a shape of a matrix in row and column directions;
a word line extending in the row direction for connecting the control terminals of the selection transistors of the memory cells arranged in the same row;
a bit line extending in the column direction for connecting the other ones of the first electrodes and the second electrodes of the variable resistive elements of the memory cells arranged in the same column;
a common line extending in the row or column direction for connecting the other ends of the pair of the input and output terminals of the selection transistors of the memory cells;
a word line voltage application circuit for applying a voltage to the word line connected to the memory cell selected as a forming process target;
a forming voltage application circuit for applying a voltage required for the forming process, across the memory cell selected as the forming process target, through the bit line and the common line connected to the selected memory cell; and
a control circuit for controlling the forming voltage application circuit in such a manner that a first pulse set to be lower than a threshold voltage at which the resistance of the variable resistive element is lowered, is applied to between the first and second electrodes of the variable resistive element selected as the forming process target, and then continuously a second pulse having the same polarity as that of the first pulse and set to be not lower than the threshold voltage is applied to between the first and second electrodes of the variable resistive element.
8. The non-volatile semiconductor memory device according to claim 7 , wherein
the forming voltage application circuit applies the second pulse to one variable resistive element, and simultaneously applies the first pulse to at least one other variable resistive element in which the forming process is not yet completed, among the variable resistive elements selected as the forming process target.
9. The non-volatile semiconductor memory device according to claim 8 , wherein
the forming voltage application circuit applies the second pulse to one variable resistive element, and simultaneously applies the first pulse previously to all the other variable resistive elements in which the forming process is not yet completed, among the variable resistive elements selected as the forming process target.
10. The non-volatile semiconductor memory device according to claim 7 , wherein
the first pulse has a gradually increasing voltage amplitude.
11. The non-volatile semiconductor memory device according to claim 7 , wherein
the variable resistor comprises a metal oxide showing n-type conductivity.
12. The non-volatile semiconductor memory device according to claim 11 , wherein
the variable resistor comprises a metal oxide selected from Ti, Ta, Hf, and Zr.
13. The non-volatile semiconductor memory device according to claim 7 , wherein
a work function of the first electrode is 4.5 eV or less, and a work function of the second electrode is 4.5 eV or more.