IP Library › Granted Patent US 8,737,554
Granted Patent B2
US 8,737,554 · App. 13/326,205 · Granted May 27, 2014

Pulse-signal recovering device with time-interleaving scheme

Inventors: Seong-Do Kim (Daejeon, KR); Pil Jae Park (Daejeon, KR); Sung Chul Woo (Seoul, KR); Hyun Kyu Yu (Daejeon, KR)
Assignee: Electronics and Telecommunications Research Institute
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Quick Facts
Patent No.
US 8,737,554
App. No.
13/326,205
Granted
May 27, 2014
Kind
B2
Abstract

Disclosed is a pulse-signal recovering device with a time-interleaving scheme. Exemplary embodiments of the present invention can improve receive performance of a radar so as to shorten pre-scanning time for roughly determining presence and absence of objects and time consumed to recover received pulse signals in the radar receiver with the sub-sampling scheme by simultaneously sensing signal levels of the received pulse signals at several positions and improve a signal to noise ratio by increasing an averaging rate with respect to the number of same received pulses.

Claims (15)

1. A pulse-signal recovering device, comprising:

a plurality of sampling blocks configured to sample a received signal and to output a plurality of sampled signals;

a sampling clock generator configured to generate a plurality of sampling clocks that have a same pulse repetition interval and have different time delays, the plurality of sampling clocks being input to corresponding sampling blocks, respectively, at different times; and

a multiplexer configured to receive the plurality of sampled signals and to output a recovered signal corresponding to the received signal,

wherein the received signal is detected at the different times determined by the plurality of sampling clocks.

2. The pulse-signal recovering device of claim 1 , wherein the received signal is an impulse signal.

3. The pulse-signal recovering device of claim 1 , wherein each of the sampling blocks includes a track and hold unit (T/H).

4. The pulse-signal recovering device of claim 1 , wherein the plurality of sampling blocks are sampling blocks with a sub-sampling scheme.

5. The pulse-signal recovering device of claim 1 , wherein the sampling clock generator includes a plurality of delay buffers configured to generate the plurality of sampling clocks.

6. The pulse-signal recovering device of claim 1 , further comprising an analog-digital converter configured to convert the recovered signal into a digital signal.

7. A pulse-signal recovering device, comprising:

a plurality of sampling blocks configured to receive same receive signals;

a sampling clock generator configured to generate a plurality of sampling clocks each of which is input to a corresponding sampling block of the plurality of sampling blocks, the plurality of sampling clocks having the same pulse repetition interval and having different time delays;

a multiplexer configured to multiplex a plurality of sampling signals output from the plurality of sampling blocks and output recover signals corresponding to the receive signals; and

an analog-digital converter configured to convert an output signal of the multiplexer into a digital signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2011
From: KIM, SEONG-DO; PARK, PIL JAE; WOO, SUNG CHUL; YU, HYUN KYU
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 027401/0534 →
Priority Claims (1)
KR 10-2010-0127576 · Dec 14, 2010 · national
Continuity (1)
Related Publication 20120148002A1 · Jun 14, 2012