Semiconductor package and method of manufacturing the same
View Patent ↗A semiconductor package including: a lead frame including a chip attachment unit and a lead unit; a semiconductor chip that is mounted on the chip attachment unit of the lead frame; a wire that electrically connects the semiconductor chip to the lead unit; an insulation layer formed in the lead frame under the chip attachment unit; and an encapsulant that seals an upper portion of the lead frame, the semiconductor chip, and the wire, wherein the lead unit does not protrude to the outside of the encapsulant.
1. A semiconductor package comprising:
a lead frame comprising a chip attachment unit, a lead unit, and an opening formed between the chip attachment unit and the lead unit;
a semiconductor chip that is mounted on the chip attachment unit of the lead frame;
a wire that electrically connects the semiconductor chip to the lead unit;
an insulation layer formed in a recess in the lead frame under the chip attachment unit;
an encapsulant that seals an upper portion of the lead frame, the semiconductor chip, and the wire; and
a second insulation layer formed in a portion under the lead unit,
wherein the lead unit does not protrude to the outside of the encapsulant,
wherein the encapsulant is formed to completely cover the lead unit of the lead frame, and one of the side walls of the lead unit and encapsulant have the same vertical plane,
wherein an upper surface of the lead unit is an inner connection lead that is connected to the semiconductor chip, and a lower surface of the lead unit is an outer connection lead that is connected to an external apparatus.
2. The semiconductor package of claim 1 , wherein the semiconductor package is a Quad Flat No-lead (QFN) package or a Micro Lead Frame (MLF) package.