IP Library Granted Patent US 8,742,572
Granted Patent B2
US 8,742,572 · App. 13/675,523 · Granted Jun 3, 2014

Microelectronic devices and methods for manufacturing microelectronic devices

Inventor: Teck Kheng Lee (Singapore, SG)
Assignee: Micron Technology, Inc.
H01L23/5226H01L24/83H01L21/3128H01L23/481H01L21/561H01L24/97H01R43/16
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Quick Facts
Patent No.
US 8,742,572
App. No.
13/675,523
Granted
Jun 3, 2014
Kind
B2
Abstract

Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes forming a plurality of through holes in a substrate with the through holes arranged in arrays, and attaching a plurality of singulated microelectronic dies to the substrate with an active side of the individual dies facing toward the substrate and with a plurality of terminals on the active side of the individual dies aligned with corresponding holes in the substrate. The singulated dies are attached to the substrate after forming the holes in the substrate.

Claims (41)

1. A plurality of microelectronic devices, comprising:

a rigid substrate having a plurality of holes arranged in arrays and a plurality of conductive traces, the substrate having a first side and a second side opposite from the first side;

a first conductive material having a first surface facing the first side of the substrate, and a second surface facing away from the first surface;

a second conductive material having a first face and a second face facing away from the first face, the first face directly containing the second surface of the first material, and the second conductive material at least partially conforming to the individual holes;

a plurality of electrical couplers directly contacting corresponding traces at the first side of the substrate; and

a plurality of singulated microelectronic dies at the second side of the substrate, the individual dies including an active side facing toward the substrate, a plurality of terminals disposed on the active side and aligned with corresponding holes, a back side opposite the active side, and a plurality of ends extending between the active side and the back side, wherein the second conductive material directly contacts the individual terminals.

2. The microelectronic devices of claim 1 wherein the substrate comprises a partially cured substrate.

3. The microelectronic devices of claim 1 wherein the substrate comprises a preformed substrate.

4. The microelectronic devices of claim 2 wherein the partially cured substrate comprises a substrate having preformed through-holes.

5. The microelectronic devices of claim 1 wherein:

the substrate comprises a dielectric substrate; and

the microelectronic devices further comprise an adhesive layer coupling the dies to the dielectric substrate.

6. The microelectronic devices of claim 1 wherein the individual dies are attached to the substrate without an adhesive positioned between the dies and the substrate.

7. The microelectronic devices of claim 1 wherein the substrate comprises a pre-preg material.

8. The microelectronic devices of claim 1 , further comprising solder mask at the first side of the substrate.

9. The microelectronic devices of claim 8 wherein the solder mask contacts the conductive links at the first side of the substrate.

10. The microelectronic devices of claim 1 , further comprising an encapsulant between adjacent dies, the encapsulant encasing at least a portion of the ends of the dies.

11. A plurality of microelectronic devices, comprising:

a rigid substrate having a plurality of preformed holes arranged in arrays and a plurality of conductive traces, the substrate having a first side and a second side opposite from the first side;

a first conductive material having a first surface facing the first side of the substrate, and a second surface facing away from the first surface;

a second conductive material having a first face and a second face facing away from the first face, the first face directly containing the second surface of the first material, and the second conductive material at least partially conforming to the individual holes;

an electrical coupler directly contacting the trace at the first side of the substrate;

a solder mask covering the plurality of conductive links at the first side of the substrate;

a plurality of singulated microelectronic dies at the second side of the substrate, the individual dies including an active side facing toward the substrate, a plurality of terminals disposed on the active side and aligned with corresponding holes, a back side opposite the active side, and a plurality of ends extending between the active side and the back side, wherein the second conductive material directly contacts the individual terminals; and

an encapsulant between adjacent dies, the encapsulant encasing at least a portion of the ends of the dies.

12. A method for manufacturing microelectronic devices, the method comprising:

providing a substrate having a dielectric layer with a first side and a second side facing away from the first side, the substrate having a plurality of traces and a plurality of through holes arranged in arrays;

placing first conductive material at the first side of the substrate;

placing second conductive material in direct contact with the first conductive material and in the through holes to form conductive links, wherein individual conductive links are in direct contact with corresponding traces at the first side of the substrate;

attaching a plurality of microelectronic dies to the substrate with an active side of the individual dies facing toward the second side of the substrate and with a plurality of terminals on the active side of the individual dies aligned with corresponding through holes in the substrate, wherein the dies are attached to the substrate after forming the through holes in the substrate; and

attaching a plurality of electrical couplers in direct contact with corresponding conductive traces at the first side of the substrate.

13. The method of claim 12 wherein the individual dies further comprise a back side opposite the active side and a plurality of ends extending between the active side and the back side, and wherein the method further comprises:

curing the substrate after attaching the dies to the substrate; and

placing an encapsulant between adjacent dies to encase at least a portion of the ends of the dies.

14. The method of claim 12 wherein providing the substrate comprises forming the through holes in a partially cured substrate.

15. The method of claim 12 wherein providing the substrate comprises forming the through holes in a pre-preg material.

16. The method of claim 12 wherein attaching the microelectronic dies to the substrate comprises coupling singulated dies to the substrate without an adhesive positioned between the substrate and the dies.

17. The method of claim 12 , further comprising curing the substrate after attaching the dies to the substrate.

18. The method of claim 12 , further comprising laser drilling the through holes in the substrate prior to providing the substrate.

19. The method of claim 12 , further comprising punching the through holes in the substrate prior to providing the substrate.

20. The method of claim 12 , further comprising placing a dielectric material at the first side of the substrate over at least one conductive link.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Priority Claims (1)
SG 200605271-6 · Aug 4, 2006 · national
Continuity (3)
Continuation 12474465 · May 29, 2009
Division 11515090 · Aug 31, 2006
Related Publication 20130181356A1 · Jul 18, 2013