IP Library › Granted Patent US 8,742,766
Granted Patent B2
US 8,742,766 · App. 14/040,945 · Granted Jun 3, 2014

Stacked via structure for metal fuse applications

Inventors: Griselda Bonilla (Fishkill, NY); Kaushik Chanda (Santa Clara, CA); Ronald G. Filippi (Wappingers Falls, NY); Stephan Grunow (Poughkeepsie, NY); Naftali E. Lustig (Croton on Hudson, NY); Andrew H. Simon (Fishkill, NY); Ping-Chuan Wang (Hopewell Junction, NY)
Assignee: International Business Machines Corporation
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Quick Facts
Patent No.
US 8,742,766
App. No.
14/040,945
Granted
Jun 3, 2014
Kind
B2
Abstract

A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Claims (8)

1. A method for electrically detecting failures in a conductive via and a conductive line, comprising the steps of:

forcing current through a fuse structure between a positive current connection and a negative current connection;

measuring voltage over each of a first voltage connection and a second voltage connection in said fuse structure; and

detecting a failure in one of a conductive via and a conductive line;

wherein failure occurs in the conductive via if an open circuit exists at both the first and second voltage connections such that there is no current flow at the voltage connections when current is forced; and

wherein a failure occurs in the conductive line if an open circuit exists at only one of the first and second voltage connections such that there is no current flow at one of the voltage connections and an open circuit does not exist at the other when current is forced.

2. The method of claim 1 , wherein the positive current connection is located on a first conductive line and the negative current connection is located on one of a conductor and a second conductive line.

3. The method of claim 1 , wherein the first voltage connection is located on a first conductive line and the second voltage connection is located on one of a conductor and a second conductive line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2013
From: BONILLA, GRISELDA; CHANDA, KAUSHIK; FILIPPI, RONALD G.; GRUNOW, STEPHAN; LUSTIG, NAFTALI E.; SIMON, ANDREW H.; WANG, PING-CHUAN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 031307/0012 →
Continuity (2)
Division 13074407 · Mar 29, 2011
Related Publication 20140028325A1 · Jan 30, 2014