IP Library › Granted Patent US 8,743,095
Granted Patent B2
US 8,743,095 · App. 13/395,223 · Granted Jun 3, 2014

Electronic apparatus and display panel

Inventors: Hiroyuki Moriwaki (Osaka, JP); Mayuko Sakamoto (Osaka, JP); Kenichi Ishii (Osaka, JP)
Assignee: Sharp Kabushiki Kaisha
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Quick Facts
Patent No.
US 8,743,095
App. No.
13/395,223
Granted
Jun 3, 2014
Kind
B2
Abstract

A display device as an electronic apparatus in accordance with the present invention includes a clock signal wiring ( 104 ) for connecting to a source driver circuit; a power supply wiring ( 105 ) formed at a position where the power supply wiring ( 105 ) does not overlap with a projection plane of the clock signal wiring ( 104 ), so as to sandwich at least an insulating layer with a layer in which the clock signal wiring ( 104 ) is formed; and a capacitive electrode ( 109 ) electrically connected to the clock signal wiring ( 104 ). The capacitive electrode ( 109 ) is formed so as to overlap at least partially with a projection plane of the power supply wiring ( 105 ). A capacitance ( 301 ) is formed between the capacitive electrode ( 109 ) and the power supply wiring ( 105 ).

Claims (40)

1. An electronic apparatus having an integrated electronic circuit, comprising:

an input/output signal wiring for inputting or outputting a signal to or from the electronic circuit;

a conductive film formed at a position where the conductive film does not overlap with a projection plane of the input/output signal wiring, so as to sandwich at least an insulating layer with a layer in which the input/output signal wiring is formed; and

a capacitive electrode electrically connected to the input/output signal wiring,

the capacitive electrode being formed so as to overlap at least partially with a projection plane of the conductive film.

2. The electronic apparatus as set forth in claim 1 , wherein:

the capacitive electrode is formed so that an entire electrode surface of the capacitive electrode is located within the projection plane of the conductive film.

3. The electronic apparatus as set forth in claim 1 , wherein:

the capacitive electrode is formed in a same layer as the input/output signal wiring.

4. The electronic apparatus as set forth in claim 1 , wherein:

the capacitive electrode is composed of a plurality of divided capacitive electrodes insulated from each other,

each of the divided capacitive electrodes constituting the same capacitive electrode being connected to the same input/output signal wiring via each connecting wiring.

5. The electronic apparatus as set forth in claim 1 , wherein:

the conductive film is a power supply wiring for supplying the electronic circuit with power.

6. The electronic apparatus as set forth in claim 1 , wherein:

the conductive film is a part of a light shielding film formed in the electronic circuit.

7. The electronic apparatus as set forth in claim 6 , wherein:

the light shielding film is connected to the power supply wiring for supplying the electronic circuit with power.

8. The electronic apparatus as set forth in claim 1 , wherein:

the conductive film is a part of a transparent conductive film for forming pixels of the electronic circuit.

9. The electronic apparatus as set forth in claim 8 , wherein:

the transparent conductive film is connected to the power supply wiring for supplying the electronic circuit with power.

10. The electronic apparatus as set forth in claim 8 , wherein:

the transparent conductive film is provided on a liquid crystal display panel including a pixel electrode substrate and a counter substrate facing the pixel electrode substrate, the transparent conductive film being provided on the pixel electrode substrate and being electrically connected to a counter electrode provided on the counter substrate via a conductive member.

11. The electronic apparatus as set forth in claim 1 , wherein:

the input/output signal wiring is a clock signal wiring for supplying the electronic circuit with a clock.

12. The electronic apparatus as set forth in claim 1 , wherein:

the input/output signal wiring is an output signal wiring for outputting an output signal from the electronic circuit to the liquid crystal display panel.

13. An electronic apparatus having an integrated electronic circuit, comprising:

an input/output signal wiring for inputting or outputting a signal to or from the electronic circuit;

a conductive film formed at a position where the conductive film does not overlap with a projection plane of the input/output signal wiring, so as to sandwich at least an insulating layer with a layer in which the input/output signal wiring is formed; and

a capacitive electrode formed so as to sandwich the insulating layer with the conductive film,

the capacitive electrode being composed of a plurality of divided capacitive electrodes insulated from each other,

each of the plurality of divided capacitive electrodes being connected, via the input/output signal wiring and the insulating layer, to each connecting wiring formed in a different layer,

the each connecting wiring being formed so that a part of a projection plane of the connecting wiring overlaps with the projection plane of the input/output signal wiring.

14. A display panel in which a gate driver circuit is formed on an insulating substrate, comprising:

a clock signal wiring for inputting or outputting a signal to or from the gate driver circuit;

a power supply wiring formed at a position where the power supply wiring does not overlap with a projection plane of the clock signal wiring, so as to sandwich at least an insulating layer with a layer in which the clock signal wiring is formed; and

a capacitive electrode electrically connected to the clock signal wiring,

the capacitive electrode being formed so as to overlap at least partially with a projection plane of the power supply wiring.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2012
From: MORIWAKI, HIROYUKI; SAKAMOTO, MAYUKO; ISHII, KENICHI
To: SHARP KABUSHIKI KAISHA
Reel/Frame 027837/0181 →
Priority Claims (1)
JP 2009-227532 · Sep 30, 2009 · national
Continuity (1)
Related Publication 20120169681A1 · Jul 5, 2012