Nonvolatile memory apparatus and verification method thereof

1. A nonvolatile memory apparatus comprising:

a memory cell array comprising a plurality of unit memory cells coupled between a plurality of word lines and a plurality of bit lines;

a page buffer unit configured to read data from a selected memory cell of the memory cell array and store the read data;

a controller configured to generate a reference current generation signal, a first current control signal, and a second current control signal, which correspond to the number of fail bits to be sensed and a deviation in cell current amounts flowing through the unit memory cells during a read operation, in response to a verification command; and

a fail bit sensing unit configured to receive the reference current generation signal, the first current control signal, and the second current control signal from the controller in response to the verification command, and control at least one of a reference current amount and a data read current amount of the page buffer unit.

2. The nonvolatile memory apparatus according to claim 1 , wherein the fail bit sensing unit controls the reference current amount according to the reference current generation signal and the first current control signal and decides a pass or fail.

3. The nonvolatile memory apparatus of claim 2 , wherein the fail bit sensing unit controls the data read current amount of the page buffer unit according to the second current control signal and decides a pass or fail.

4. The nonvolatile memory apparatus according to claim 1 , wherein the controller comprises:

a register configured to generate the reference current generation signal, the first current control signal, and the second current control signal, which correspond to the number of fail bits to be sensed according to the deviation in cell current amounts; and

a current control signal generator configured to provide the reference current generation signal, the first current control signal, and the second current control signal to the fail bit sensing unit.

5. The nonvolatile memory apparatus according to claim 4 , wherein the controller further comprises a decoder configured to decode the number of fail bits to be sensed to binary bits in a designated unit.

6. The nonvolatile memory apparatus according to claim 4 , wherein the controller further comprises an error correction circuit (ECC) configured to correct an error for fail bits, and

the number of fail bits to be sensed is fixed or varied within such a range that is corrected by the ECC.

7. The nonvolatile memory apparatus according to claim 1 , wherein the fail bit sensing unit comprises:

a comparison section configured to compare the read current amount with the reference current amount to decide a pass or fail, in response to the verification command; and

an offset control section configured to vary the reference current amount or the read current amount in response to the reference current generation signal, the first current control signal, and the second current control signal.

8. The nonvolatile memory apparatus according to claim 7 , wherein the offset control section comprises:

a reference current generator configured to generate the reference current in response to the reference current generation signal provided from the controller;

a first offset current generator configured to vary the reference current amount in response to the first current control signal provided from the controller; and

a second offset current generator configured to vary the read current amount in response to the second current control signal provided from the controller.