Controlling user-added boundary scan register with TAP of IP core
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15 , test data output leads 13 , control leads 17 and an external register present, ERP lead 37 . A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.
1. A process of executing test access port instructions in an intellectual property core that contains a test access port and is free of a boundary scan register, the test access port including a test data in lead and a test data out lead, comprising:
A. sensing whether an external register present signal on an external register present lead connected to the test access port indicates the presence of a user-added boundary scan register;
B. receiving a Sample/Preload instruction in an instruction register of the test access port;
C. inhibiting operation of the intellectual property core;
D. coupling the user-added boundary scan register to the test data in lead and to the test data out lead; and
E. controlling the user-added boundary scan register with the test access port of the intellectual property core to capture and shift out functional signals flowing though the boundary scan register.