Encoding/decoding apparatus and method
An encoder and a decoder employ an encoding scheme corresponding to a parity check matrix which is derivable from a bipartite protograph formed of variable nodes and check nodes, with each variable node corresponding to a codeword symbol position. The protograph has a plurality of groups of nodes, each group of nodes comprising both variable nodes and check nodes. Each of the check nodes in a group is of degree 2 and has connections to two variable nodes in the same group. The protograph also has a plurality of check nodes of degree n, where n is the number of said plurality of groups, wherein each of the plurality of check nodes has a connection to a variable node in each group such that the symbol positions in a codeword are interleaved between the groups of nodes.
1. An encoder comprising:
an input interface configured to receive a data stream;
a processor configured to map the received data stream into corresponding codewords; and
an output interface configured to output said codewords,
wherein said processor is configured to map packets of the received data stream, each packet comprising a sequence of packet symbols, into respective codewords, each codeword comprising a sequence of codeword symbols, using an encoding scheme corresponding to a parity check matrix that is derived from a bipartite protograph,
wherein the bipartite protograph comprises:
a plurality of groups of nodes, each group of nodes comprising variable nodes and a first plurality of check nodes, each variable node corresponding to a codeword symbol position, wherein each of the check nodes in the first plurality of check nodes is of degree two and is connected to two variable nodes in the same group and wherein each of the groups of nodes forms a parallel path in the bipartite protograph, wherein each variable node in the bipartite protograph belongs to one of the groups of nodes; and
a second plurality of check nodes of degree n, n being the number of said plurality of groups, wherein each of the second plurality of check nodes is connected to a variable node in each group such that the codeword symbol positions in each codeword are interleaved between the groups of nodes.
2. The encoder according to claim 1 , wherein the second plurality of check nodes of degree n consists of two check nodes.
3. The encoder according to claim 1 , wherein the second plurality of check nodes of degree n are connected to respective different symbol nodes in each group.
4. The encoder according to claim 1 , wherein the check nodes in the second plurality of check nodes are connected to a same symbol node in each group of nodes.
5. The encoder according to claim 1 , wherein the plurality of groups of nodes consists of three groups of nodes.
6. The encoder according to claim 1 , wherein the processor is further configured to adjust a coding rate by puncturing the codeword symbols while maintaining the encoding scheme.
7. The encoder according to claim 1 , wherein the processor is further configured to process the received data stream to generate the packets comprising sequences of packet symbols, with each symbol being from a Galois field of dimension q, and to map the packets into codewords formed of symbols in a Galois field of dimension q, wherein q is in the range from 32 to 256.
8. The encoder according to claim 1 , wherein at least one of the packet symbols and the codeword symbols are binary symbols.
9. The encoder according to claim 1 , wherein the encoding scheme is stored in a memory.
10. The encoder according to claim 1 , wherein non-zero values in the parity check matrix are assigned based on a Progressive Edge-Generation (PEG) algorithm.
11. A decoder comprising:
an input interface configured to receive a stream of codewords, each codeword comprising a sequence of codeword symbols;
a processor configured to decode the codewords to recover data packets; and
an output interface configured to output said data packets, each packet comprising a sequence of packet symbols,
wherein the processor is configured to recover said data packets using a parity check matrix that is derived from a bipartite protograph,
wherein the bipartite protograph comprises:
a plurality of groups of nodes, each group of nodes comprising a plurality of variable nodes and a first plurality of check nodes, each variable node corresponding to a codeword symbol position, wherein each of the check nodes in the first plurality of check nodes is of degree two and is connected to two variable nodes in the same group and wherein each of the groups of nodes forms a parallel path in the bipartite protograph, wherein each variable node in the bipartite protograph belongs to one of the groups of nodes; and
a second plurality of check nodes of degree n, n being the number of said plurality of groups, wherein each of the second plurality of check nodes is connected to a variable node in each group such that the codeword symbol positions in each codeword are interleaved between the groups of nodes.
12. The decoder according to claim 11 , wherein the second plurality of check nodes of degree n consists of two check nodes.
13. The decoder according to claim 11 , wherein the second plurality of check nodes of degree n are connected to respective different symbol nodes in each group.
14. The decoder according to claim 11 , wherein the check nodes in the second plurality of check nodes are connected to a same symbol node in each group of nodes.
15. The decoder according to claim 11 , wherein the plurality of groups of nodes consists of three groups of nodes.
16. The decoder according to claim 11 , wherein the processor is further configured to process the received data stream to generate the packets comprising sequences of packet symbols, each symbol being from a Galois field of dimension q, and to map the packets into codewords formed of symbols in a Galois field of dimension q, wherein q is in the range from 32 to 256.
17. The decoder according to claim 11 , wherein at least one of the packet symbols and the codeword symbols are binary symbols.
18. The decoder according to claim 11 , wherein the processor is further configured to execute a belief propagation algorithm to perform error detection and correction.
19. The decoder according to claim 11 , wherein a decoding scheme executed by the processor is stored in a memory.
20. The decoder according to claim 11 , wherein the processor is further configured to execute an Extended Minimum Sum (EMS) algorithm to perform error detection and correction.