Semiconductor device and method for forming the same

1. A semiconductor device, which is formed on a semiconductor substrate and comprises a metal gate, source and drain regions and contact plugs, wherein said source and drain regions are located on both sides of the metal gate and are at least partially embedded into the semiconductor substrate, the contact plugs comprise:

first contact plugs comprising a first barrier layer arranged on the source and drain regions, a tungsten layer arranged on the first barrier layer, a second barrier layer arranged on the tungsten layer, and a conductive layer arranged on the second barrier layer; and

second contact plugs comprising the second barrier layer arranged on both of the metal gate and the first contact plugs and the conductive layer arranged on the second barrier layer of the second contact plug arranged on the first contact plug,

wherein the second barrier layer and the conductive layer are arranged both in the first contact plug on the tungsten layer and in the second contact plug on the metal gate and the first contact plug, and

wherein the conductivity of the conductive layer is higher than that of the tungsten layer.

2. The semiconductor device according to claim 1 , characterized in that the conductive layer is a copper layer.

3. The semiconductor device according to claim 1 , characterized in that the individual second contact plugs are of different heights.

4. The semiconductor device according to claim 1 , characterized in that the first barrier layer is a layer of Ti and/or TiN.

5. The semiconductor device according to claim 1 , characterized in that the second barrier layer is a layer of Ta and/or TaN.

6. A method for forming a semiconductor device, comprising the steps of: forming on the semiconductor substrate a first dielectric layer and planarizing the first dielectric layer, the semiconductor substrate having a metal gate and source and drain regions formed thereon, the source and drain regions being located on both sides of the metal gate and being at least partially buried into the semiconductor substrate, and the first dielectric layer covering the source and drain regions with the metal gate exposed;

forming a first contact hole exposing part of the source and drain regions in the planarized first dielectric layer, and filling said first contact hole with a first barrier layer, a tungsten layer, a second barrier layer and a conductive layer in this order to form a third contact plug, wherein the first barrier layer is arranged on the source and drain regions, and the conductivity of the conductive layer is higher than that of the tungsten layer;

forming a second dielectric layer and planarizing the second dielectric layer, the second dielectric layer covering the metal gate, the first dielectric layer, and the third contact plug; and

forming a second contact hole in the planarized second dielectric layer so as to form a fourth contact plug after filling said second contact hole with the second barrier layer and the conductive layer, the conductivity of the conductive layer being higher than that of the tungsten layer, the conductive layer being arranged on the second barrier layer, and the second barrier layer being arranged on both of the metal gate and the third contact plug.

7. The method according to claim 6 , characterized in that the conductive layer is a copper layer.

8. The method according to claim 6 , characterized in that the first barrier layer is a layer of Ti and/or TiN.

9. The method according to claim 6 , characterized in that the second barrier layer is a layer of Ta and/or TaN.