Semiconductor storage device, method of controlling the same, and error correction system
A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).
1. A apparatus comprising:
a storage device comprising:
a memory module which stores an encoded code word,
a controller which includes a hardwired ECC module which is configured to decode the code word read from the memory module to correct an error included in the code word,
a host device comprising a processor which is configured to receive the code word, and to decode the code word, by executing ECC software, when the error included in the code word is not correctable by the ECC module, wherein an error correcting capability of decoding is stronger with decoding by the processor than decoding by the ECC module.
2. The apparatus according to claim 1 , wherein the memory module comprises NAND Flash memory and a bit length of the code word is an integral multiple of a bit length of the page size of the NAND Flash memory.
3. The apparatus according to claim 1 , wherein the code word comprises a first portion and a second portion, and the ECC module uses the first portion for decoding and the processor uses the second portion for decoding.
4. A storage device connectable to a host device, comprising:
a memory module which stores an encoded code word,
a controller which includes a hardwired ECC module which is configured to decode the code word read from the memory module to correct an error included in the code word, and to output the code word to the host device when the error included in the code word is not correctable, so that a processor in the host device is capable of decoding the code word, by executing ECC software.
5. The device according to claim 4 , wherein the memory module comprises NAND Flash memory and a bit length of the code word is an integral multiple of a bit length of a page size of the NAND Flash memory.
6. The device according to claim 5 , wherein the code word comprises a first portion and a second portion, and the ECC module uses the first portion for decoding and the processor uses the second portion for decoding.