Encoding method of TLDPC codes utilizing treillis representations of the parity check equations and associated encoding device

1. An encoding method associating p redundancy data bits with k information data bits to determine code words with a block length of n=p+k data bits, the code words being of tail-biting trellis low density parity check type, said method comprising the steps:

implementing a degree distribution profile of n data bits defining a base code word comprising multiple replicas of the n data bits with respect to the degree distribution, the base code word being represented by a two-state trellis formed of sections with positions accommodating data bits of the base code word whereby the number of positions of a section is denoted as the degree of the section,

making a partition of the base code word trellis into p intersecting regular parts of triple sections representing p parity check equations,

arranging the base code word data bits into the positions of the two-state trellis with respect to the degree of the sections and of the data bits as well as pre-determined permutation rules,

successively recovering the values of all unknown redundancy data bits, one regular part of triple section after another, using a redundancy data bit value as a known value after being recovered from previous regular parts of triple sections.

2. The method according to claim 1 , wherein a degree distribution profile comprises different degrees and the different degrees of the distribution profile are assigned successively, first to the redundancy data bits and then to the information data bits, starting with the lowest degree.

3. The method according to claim 1 , wherein the permutation rules specify that, for all successive parts, there is, at most, one unknown redundancy data bit value when a redundancy data bit value is a known data bit value if recovered from a previous regular part of triple section.

4. The method according to claim 3 , wherein some sections are of degree one, all the sections except the ones of degree one being of degree two, wherein the degree distribution profile of the n data bits is such that a number λ 1 of degree one data bits is equal to the number of degree one sections, wherein said pre-determined permutation rules are the following:

all but one degree one sections of the trellis are filled with redundancy data bits and the remaining unfilled degree one section cannot be any of the first or the last two degree one sections of the trellis,

the remaining unfilled degree one section is filled with a degree two redundancy data bit value,

all sections of degree two or more are filled with data bits of degree two or more except of a single position at a last degree two section that is filled with the remaining degree one data bit value,

each of the n-k trellis triple sections that represent parity check equations involve just one unknown data bit value,

if the first copy of a redundancy data bit value of degree higher than one is placed on a trellis section i where i(mod 2)=0, then its one or more replicas are placed on one or more trellis sections j>i, otherwise if i(mod 2)=1 then the one or more replicas are placed at one or more trellis sections j>(i+1).

5. The method according to claim 1 , wherein one permutation rule specifies that, for all successive regular parts of triple sections, a redundancy data bit value is a known data bit value if recovered from a previous regular part and there is at most, one unknown redundancy data bit value arranged at one position of the last two sections of the regular part, except for the last regular part wherein the unknown data bit value is arranged at one position of the first section, and wherein for a first regular part the method uses a tail-biting termination of the base code trellis to determine modulo-two summation of two other unknown distinct redundancy data bits arranged at the first section of the first regular part.

6. The method according to claim 5 , wherein all sections are degree two, wherein said pre-determined permutation rules further comprise the following:

the first occurrence of each redundancy data bit value is associated with the last two sections of the regular parts and these last two sections are associated with only one unknown,

all sections of degree two or more are filled with data bits of degree two or more except of a single position at the last degree two section that is filled with the remaining degree one data bit value,

each of the n-k trellis triple sections that represent parity check equations involve just one unknown data bit value,

if the first copy of a redundancy data bit value of degree higher than one is placed on the trellis section i where i(mod 2)=0, then its one or more replicas are placed on one or more trellis sections j>i, otherwise if i(mod 2)=1 then the one or more replicas are placed at one or more trellis sections j>(i+1).

7. A non-transitory article of manufacture for use in a computer system comprising calculation means, having a computer usable medium, to perform an encoding method for associating p redundancy data bits with k information data bits to determine code words with a block length of n=p+k data bits, the code words being of tail-biting trellis low density parity check type, the encoding method implementing a degree distribution profile of the n data bits defining a base code word including multiple replicas of the n data bits with respect to the degree distribution, the base code word being represented by a two-state trellis formed of sections with positions accommodating data bits of the base code word whereby the number of positions of a section is denoted as the degree of the section, wherein the computer usable medium comprises a computer readable code means for:

making a partition, with the calculation means, of the base code word trellis into p intersecting regular parts of triple sections representing p parity check equations,

arranging, with the calculation means, the base code word data bits into the positions of the two-states trellis with respect to the degree of the sections and of the data bits as well as pre-determined permutation rules,

successively recovering, with the calculation means, the values of all unknown redundancy data bits, one regular part of triple section after the other, using a redundancy data bit value as a known value after being recovered from previous regular parts of triple sections.

8. A module on an encoder device for encoding code words associating p redundancy data bits with k information data bits to determine the code words with a block length of n=p+k data bits, the code words being of tail-biting trellis low density parity check type, said module comprising:

a calculating computer encoder chip,

a module for implementing a degree distribution profile of n data bits defining a base code word comprising multiple replicas of the n data bits with respect to the degree distribution, the base code word being represented by a two-state trellis formed of sections with positions accommodating data bits of the base code word whereby the number of positions of a section is denoted as the degree of the section,

a module for making a partition of the base code word trellis into p intersecting regular parts of triple sections representing p parity check equations,

a module for arranging the base code word data bits into the positions of the two-state trellis with respect to the degree of the sections and of the data bits as well as pre-determined permutation rules,

a module for successively recovering the values of all unknown redundancy data bits, one regular part of triple section after another, using a redundancy data bit value as a known value after being recovered from previous regular parts of triple sections.

9. An encoding device comprising at least one module for encoding code words according to claim 8 .

10. A transmitter comprising an encoding device according to claim 9 .

11. A telecommunication system comprising a transmitter according to claim 10 .