IP Library › Granted Patent US 8,753,966
Granted Patent B2
US 8,753,966 · App. 13/745,387 · Granted Jun 17, 2014

Method for fabricating buried gates using pre landing plugs

Inventors: Jum-Yong Park (Icheon-si, KR); Jong-Han Shin (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
H01L21/28017H01L29/4236H01L27/10876H01L27/10897H01L27/10823H01L27/105H01L27/10894
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Quick Facts
Patent No.
US 8,753,966
App. No.
13/745,387
Granted
Jun 17, 2014
Kind
B2
Abstract

A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.

Claims (25)

1. A method for fabricating a semiconductor device, comprising:

forming a plug conductive layer over an entire surface of a substrate;

etching the plug conductive layer to form landing plugs;

etching the substrate between the landing plugs to form a trench;

forming a gate insulation layer over the etched substrate;

forming a buried gate over the gate insulation layer to fill a lower portion of the trench; and

forming a sealing layer over the buried gate to fill an upper portion of the trench.

2. The method of claim 1 , further comprising:

forming a contact hole exposing a surface of each of the landing plugs.

3. The method of claim 1 , wherein the sealing layer comprises one selected from the group consisting of an oxide layer, a nitride layer and a double-layered structure comprising a nitride layer and an oxide layer.

4. The method of claim 1 , wherein the plug conductive layer comprises a metal layer or a polysilicon layer.

5. The method of claim 1 , wherein the forming of each of the landing plugs and the trench is performed by using a hard mask layer as an etch barrier.

6. A method for fabricating a semiconductor device, comprising:

forming a device isolation layer in a substrate;

forming a plug conductive layer over an entire surface of the substrate;

etching the plug conductive layer to form landing plugs;

etching the substrate between the landing plugs to form a trench;

forming a gate insulation layer over the etched substrate;

forming a buried gate over the gate insulation layer to fill a lower portion of the trench; and

forming a sealing layer over the buried gate to fill an upper portion of the trench.

7. The method of claim 6 , further comprising:

forming a contact hole exposing a surface of each of the landing plugs.

8. The method of claim 6 , wherein the sealing layer comprises one selected from the group consisting of an oxide layer, a nitride layer and a double-layered structure comprising a nitride layer and an oxide layer.

9. The method of claim 6 , wherein the plug conductive layer comprises a metal layer or a polysilicon layer.

10. The method of claim 6 , wherein the forming of each of the landing plugs and the trench is performed by using a hard mask layer as an etch barrier.

Priority Claims (1)
KR 10-2009-0060879 · Jul 3, 2009 · national
Continuity (2)
Continuation 12613708 · Nov 6, 2009
Related Publication 20130137258A1 · May 30, 2013