Vertical stacking of field effect transistor structures for logic gates
Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.
1. An apparatus comprising:
a semiconductor substrate;
a first Field Effect Transistor (FET) on the semiconductor substrate, the first FET further comprising a first source, a first drain, a first gate dielectric, a first body, and a first gate electrode, the first gate electrode coupled to a first source of a first logical signal;
a second FET, the second FET further comprising a second source, a second drain, a second gate dielectric, a second body, and a second gate electrode, the second gate electrode coupled to a second source of a second logical signal, the second source of the second logical signal not being the first source of the first logical signal, the second gate electrode being above the first gate electrode relative to a top surface of the semiconductor substrate;
a first epitaxial layer of similar doping as the first drain and the first source, the first epitaxial layer grown over the first drain and the first source;
an oxide created over the first source to electrically isolate the first source from the first epitaxial layer over the first source; and
a second epitaxial layer of opposite doping as the first drain and the first source grown over the first epitaxial growth, the first epitaxial layer comprising the second drain and the second source, and the second epitaxial growth forming the second body.
2. The apparatus of claim 1 , wherein the first FET in an N-channel Field Effect Transistor (NFET) and the second FET is an NFET.
3. The apparatus of claim 1 , wherein the first FET is a P-channel Field Effect Transistor (PFET) and the second FET is a PFET.
4. The apparatus of claim 1 further comprising a lined contact hole passing through the first epitaxial layer and the oxide for providing electrical connection to the first source.
5. The apparatus of claim 4 , further comprising:
the first source electrically connected to the second source; and
the first drain electrically connected to the second drain;
the second drain electrically connected to an output;
the first source further electrically connected to a first voltage source;
a third FET of type opposite to the first and second FETs, having a third source, a third drain, and a third gate electrode;
a fourth FET of same type as the third FET, having a fourth source, a fourth drain, and a fourth gate electrode;
the third source electrically connected to a second voltage source;
the third drain electrically connected to the fourth source; and
the fourth drain connected to the output.