Through-silicon via self-routing circuit and routing method thereof
View Patent ↗A through-silicon via self-routing circuit includes a plurality of through-silicon vias (TSVs) and a plurality of planar die. The plurality of planar die are connected by the plurality of TSVs. And each one of the plurality of planar die includes a built-in self-tester, a built-in self-routing switching network, and a core circuit. The built-in self-tester has a plurality of valid-bit leads and a plurality of through-silicon via leads to connect the plurality of TSVs. The built-in self-routing switching network is connected to the built-in self-tester, for selecting from the plurality of TSVs for conducting. The core circuit has a to plurality of I/O leads linked to the built-in self-routing switching network.
1. A through-silicon via self-routing circuit comprising:
a plurality of through-silicon vias; and
a plurality of planar die, connected by the plurality of through-silicon vias, each one of the plurality of planar die comprising:
a built-in self-tester, having a plurality of valid-bit leads and a plurality of through-silicon via leads to connect the plurality of through-silicon vias;
a built-in self-routing switching network, connected to the built-in self-tester, whereby the built-in self-routing switching network selects from the plurality of through-silicon vias for conducting; and
a core circuit, having a plurality of I/O leads linked to the built-in self-routing switching network.
2. The through-silicon via self-routing circuit of claim 1 , wherein the built-in self-tester further comprising:
a first multiplexer, connected to one of the plurality of through-silicon vias and one of the plurality of through-silicon via leads;
a second multiplexer, connected to the first multiplexer;
a first flip-flop, connected to the second multiplexer;
an XNOR gate, connected to the first flip-flop; and
a second flip-flop, connected to the XNOR gate and one of the plurality of valid-bit leads.
3. The through-silicon via self-routing circuit of claim 1 , wherein the built-in self-routing switching network further comprising:
a switching cell, comprising:
an AND gate, connected to one of the plurality of valid-bit leads;
a switch, connected to the AND gate, one of the plurality of through-silicon via leads, and one of the plurality of I/O leads; and
a OR gate, connected to the switch and the AND gate.
4. The through-silicon via self-routing circuit of claim 3 , wherein the switching cell is an iterative logic array.
5. A routing method, applying to the through-silicon via self-routing circuit of claim 1 , the routing method comprising the steps in the order of:
deciding a priority of the core circuit;
testing the plurality of through-silicon vias by the built-in self-tester;
using the built-in self-tester to produce a plurality of valid bits, which are matched to linking the plurality of through-silicon vias; and
using the built-in self-routing switching network to select good through-silicon vias from the plurality of through-silicon vias and to link the good through-silicon vias to the core circuit.
6. The routing method of claim 5 , wherein the step of testing the plurality of through-silicon vias by the built-in self-tester further comprising:
selecting the through-silicon via leads matched to the through-silicon via;
storing and passing a through-silicon via signal to be tested; and
testing the through-silicon via signal to be tested.
7. The routing method of claim 5 , wherein the step of using the built-in self-routing switching network to select good through-silicon vias from the plurality of through-silicon vias and to link the good through-silicon vias to the core circuit comprising:
testing the valid bit;
deciding whether to link the through-silicon via; and
outputting a signal for being linked.