Capacitor charge balance system

1. A circuit, comprising:

a series arrangement of two or more capacitor stages, each stage comprising a single capacitor or a plurality of capacitors in parallel, the series arrangement configured such that each capacitor stage is supplied with charge current via a common charging terminal;

a controller configured to separately measure a stored potential of each capacitor stage in the series arrangement;

nontransitory logic to selectively remove a controlled amount of charge from each of the capacitor stages individually (discharge logic); and

nontransitory logic to operate the discharge logic to maintain each capacitor stage at a substantially equal stored potential (balancing logic) while the series arrangement is receiving the charge current from the common charging terminal.

2. The circuit of claim 1 , wherein at least one first capacitor stage of the series arrangement has a capacitance mismatched from a capacitance of a second capacitor stage of the series arrangement.

3. The circuit of claim 1 , the controller configured to operate the discharge logic to discharge at least one of the capacitor stages concurrently with charging the series arrangement of capacitor stages.

4. The circuit of claim 3 , the controller configured to detect an overcharge of one or more of the capacitor stages, and to operate the discharge logic to discharge the one or more capacitor stages that overcharge, while concurrently charging the series arrangement of capacitor stages.

5. The circuit of claim 1 , wherein the discharge logic comprises, for each capacitor stage, a switch in series with a resistance.

6. The circuit of claim 1 , wherein the discharge logic comprises, for each capacitor stage, a duty cycle modulated switch.

7. The circuit of claim 1 , the controller configured to detect an imbalance in the stored potential of two or more of the capacitor stages, and to operate the discharge logic to balance the stored potential on the two or more imbalanced capacitor stages.

8. A memory module, comprising:

a volatile memory;

a nonvolatile memory;

a series arrangement of two or more capacitor stages, each stage comprising a single capacitor or a plurality of capacitors in parallel, the series arrangement configured such that each capacitor stage is supplied with charge current via a common charging terminal;

a controller configured to separately measure a stored potential of each capacitor stage in the series arrangement;

nontransitory logic to selectively remove a controlled amount of charge from each of the capacitor stages individually (discharge logic);

nontransitory logic to operate the discharge logic to maintain each capacitor stage at a substantially equal stored potential (balancing logic) while the series arrangement is receiving the charge current from the common charging terminal; and

nontransitory logic to apply power from the series arrangement of capacitors to backup data from the volatile memory to the nonvolatile memory upon a failure of primary power to the memory module.

9. The memory module of claim 8 , wherein at least one first capacitor stage of the series arrangement has a capacitance mismatched from a capacitance of a second capacitor stage of the series arrangement.

10. The memory module of claim 8 , the controller configured to operate the discharge logic to discharge at least one of the capacitor stages concurrently with charging the series arrangement of capacitor stages.

11. The memory module of claim 10 , the controller configured to detect an overcharge of one or more of the capacitor stages, and to operate the discharge logic to discharge the one or more capacitor stages that overcharge, while concurrently charging the series arrangement of capacitor stages.

12. The memory module of claim 8 , wherein the discharge logic comprises, for each capacitor stage, a switch in series with a resistance.

13. The memory module of claim 8 , wherein the discharge logic comprises, for each capacitor stage, a duty cycle modulated switch.

14. The memory module of claim 8 , the controller configured to detect an imbalance in the stored potential of two or more of the capacitor stages, and to operate the discharge logic to balance the stored potential on the two or more imbalanced capacitor stages.

15. A method of managing the charge stored by a series arrangement of capacitor stages, each stage comprising a single capacitor or a plurality of capacitors in parallel, the method comprising:

supplying each capacitor stage with charge current via a common charging terminal;

separately measuring a stored potential of each capacitor stage in the series arrangement;

selectively removing a controlled amount of charge from each of the capacitor stages individually while the series arrangement is receiving the charge current from the common charging terminal; and

maintaining each capacitor stage at a substantially equal stored potential.

16. The method of claim 15 , further comprising:

mismatching the capacitance of at least one first capacitor stage of the series arrangement from a capacitance of a second capacitor stage of the series arrangement.

17. The method of claim 15 , further comprising:

discharging at least one of the capacitor stages concurrently with charging the series arrangement of capacitor stages.

18. The method of claim 17 , further comprising:

detecting an overcharge of one or more of the capacitor stages, and discharging the one or more capacitor stages that overcharge, while concurrently charging the series arrangement of capacitor stages.

19. The method of claim 15 , further comprising:

for each capacitor stage, operating a switch in series with a resistance to discharge the capacitor stage.

20. The method of claim 15 , further comprising:

operating a duty cycle modulated switch to discharge each capacitor stage.

21. The method of claim 15 , further comprising:

detecting an imbalance in the stored potential of two or more of the capacitor stages, and balancing the stored potential of the two or more imbalanced capacitor stages by discharging at least one of the two or more imbalanced capacitor stages.