Frequency synthesis methods and systems
Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority.
1. A system, comprising:
a first circuit portion, including a first phase locked loop (PLL), to generate a substantially fixed-frequency first interim clock from an input reference clock; and
a second circuit portion, including a second PLL, to generate a first output clock from the first interim clock, wherein the second circuit portion is configurable with respect to multiple parameters to generate the first output clock at one of multiple selectable frequencies; and
a control portion to select parameter values to apply to the second circuit portion, including to,
identify parameter values for which a frequency difference between the first output clock and a desired frequency is equal to or less than a threshold value, as a first priority,
identify parameter values for which first output clock jitter is lowest, as a second priority, and
identify parameter values for which the frequency difference between the first output clock and the desired frequency is lowest, as a third priority.
2. The system of claim 1 wherein:
the second circuit portion is configurable at least with respect to parameters N, R, and P;
a frequency of the first output clock is a function of a product of the frequency of the first interim clock and N/(R*P); and
the control portion is configured to select from amongst integer and half integer values of N and R.
3. The system of claim 2 , wherein:
the control portion is further configured to select from amongst even integer values of P.
4. The system of claim 1 , wherein:
the first circuit portion is configured to output a second interim clock; and
the second circuit portion is controllable to generate the first output clock from a selected one of the first and second interim clocks.
5. The system of claim 1 , wherein:
the input reference clock has one of multiple frequencies; and
the first circuit portion is controllable to generate the first interim clock at the substantially fixed frequency for each of the multiple frequencies of the input reference clock.
6. The system of claim 1 , wherein:
the first PLL includes an inductive-capacitive voltage-controlled oscillator; and
the second PLL includes one or more of a self-biased voltage-controlled oscillator and a digitally-controlled oscillator.
7. The system of claim 1 , wherein:
the second PLL includes a self-biased voltage-controlled oscillator (SB-VCO); and
the control portion includes a capacitive control portion to increase a capacitance exposed to self-bias circuitry of the SB-VCO when an operating frequency of the SB-VCO is at or below a threshold.
8. A computer system, comprising:
an integrated circuit (IC) die including one or more processors, a graphics engine, a media interface to re-time display data from the graphics engine based on a data transmit clock, and a frequency synthesizer to derive the data transmit clock from an off-die sourced display bus clock;
wherein the frequency synthesizer includes,
a first circuit portion, including a first phase locked loop (PLL) to generate a substantially fixed-frequency first interim clock from the display bus clock; and
a second circuit portion, including a second PLL, to generate the data transmit clock from the first interim clock, wherein the second circuit portion is configurable with respect to multiple parameters to generate the first output clock at one of multiple selectable frequencies;
wherein the second circuit portion is configurable at least with respect to parameters N, R, and P;
wherein a frequency of the data transmit clock is a function of a product of the frequency of the first interim clock and N/(R*P); and
wherein the control portion is configured to select from amongst integer and half integer values of N and R and from even integer values of P.
9. The computer system of claim 8 , wherein the IC die further includes a control portion to select parameters to apply to the second circuit portion, including to,
identify parameter values for which a frequency difference between the data transmit clock and a desired frequency is equal to or less than a threshold value, as a first priority,
identify parameter values for which data transmit clock jitter is lowest, as a second priority, and
identify parameter values for which the frequency difference between the data transmit clock and the desired frequency is lowest, as a third priority.
10. The computer system of claim 8 , wherein:
the first PLL includes an inductive-capacitive voltage-controlled oscillator; and
the second PLL includes one or more of a self-biased voltage-controlled oscillator and a digitally-controlled oscillator.
11. The computer system of claim 8 , wherein:
the input reference clock has one of multiple frequencies; and
the first circuit portion is controllable to generate the first interim clock at the substantially fixed frequency for each of the multiple frequencies of the input reference clock.
12. A system, comprising:
a first circuit portion, including a first phase locked loop (PLL), to generate a substantially fixed-frequency first interim clock from an input reference clock; and
a second circuit portion, including a second PLL, to generate a first output clock from the first interim clock, wherein the second circuit portion is configurable with respect to multiple parameters to generate the first output clock at one of multiple selectable frequencies;
wherein the second circuit portion is configurable at least with respect to parameters N, R, and P;
wherein a frequency of the first output clock is a function of a product of the frequency of the first interim clock and N/(R*P); and
wherein the control portion is configured to select from amongst integer and half integer values of N and R, and amongst even integer values of P.
13. The system of claim 12 , further including a control portion to select parameter values to apply to the second circuit portion, including to,
identify parameter values for which a frequency difference between the first output clock and a desired frequency is equal to or less than a threshold value, as a first priority,
identify parameter values for which first output clock jitter is lowest, as a second priority, and
identify parameter values for which the frequency difference between the first output clock and the desired frequency is lowest, as a third priority.
14. The system of claim 12 , wherein:
the first circuit portion is configured to output a second interim clock; and
the second circuit portion is controllable to generate the first output clock from a selected one of the first and second interim clocks.
15. The system of claim 12 , wherein:
the input reference clock has one of multiple frequencies; and
the first circuit portion is controllable to generate the first interim clock at the substantially fixed frequency for each of the multiple frequencies of the input reference clock.
16. The system of claim 12 , wherein:
the first PLL includes an inductive-capacitive voltage-controlled oscillator; and
the second PLL includes one or more of a self-biased voltage-controlled oscillator and a digitally-controlled oscillator.
17. The system of claim 12 , wherein:
the second PLL includes a self-biased voltage-controlled oscillator (SB-VCO); and
the control portion includes a capacitive control portion to increase a capacitance exposed to self-bias circuitry of the SB-VCO when an operating frequency of the SB-VCO is at or below a threshold.