IP Library Granted Patent US 8,756,548
Granted Patent B2
US 8,756,548 · App. 13/464,873 · Granted Jun 17, 2014

Computing system with hardware reconfiguration mechanism and method of operation thereof

Inventor: Peter J Zievers (Naperville, IL)
Assignee: Xcelemor, Inc.
G06F17/5027G06F17/5054G06F9/24G06F1/24G06F15/177
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Quick Facts
Patent No.
US 8,756,548
App. No.
13/464,873
Granted
Jun 17, 2014
Kind
B2
Abstract

A method for operating a computing system includes: receiving an application-tree for instantiating an application in a reconfigurable hardware device; operating a kernel unit for determining an unoccupied logic-sector within a reconfigurable hardware device; calculating a layout section from the application-tree according to the unoccupied logic-sector for instantiating a fragment circuitry corresponding to the layout section; and determining a system table for connecting the fragment circuitry to other portions of the application to form the application having the fragment circuitry.

Claims (75)

1. A method for operating a computing system comprising:

receiving an application-tree for instantiating an application in a reconfigurable hardware device;

operating a kernel unit for determining an unoccupied logic-sector within a reconfigurable hardware device;

calculating a layout section from the application-tree according to the unoccupied logic-sector for instantiating a fragment circuitry corresponding to the layout section; and

determining a system table for connecting the fragment circuitry to other portions of the application to form the application having the fragment circuitry including scheduling a time slot in a machine reservation for incorporating the fragment circuitry instantiated until the time slot.

2. The method as claimed in claim 1 further comprising:

receiving an application-descriptor for instantiating the application;

calculating a further layout section having an instantiation condition based on the application-descriptor for implementing a different portion of the application; and

forming a further circuitry for implementing the different portion of the application when the instantiation condition has been met.

3. The method as claimed in claim 1 further comprising:

determining a further-available logic-sector for implementing a different portion of the application through a coupled kernel instance;

calculating a further layout section having a circuit characteristic for instantiating a further circuitry corresponding to the further layout section;

sending the further layout section for forming the further circuitry through the coupled kernel instance to implement the different portion of the application; and

adjusting the system table for forming the application having the further circuitry.

4. The method as claimed in claim 1 further comprising:

calculating a further-available logic-sector for reallocating contents within the reconfigurable hardware device; and

adjusting the system table for relocating the fragment circuitry into the further-available logic-sector.

5. The method as claimed in claim 1 further comprising:

recalculating the fragment circuitry for rearranging the application; and

adjusting the system table for implementing the fragment circuitry after the recalculating.

6. The method as claimed in claim 1 wherein:

operating the kernel unit includes operating the kernel unit for determining the unoccupied logic-sector in the reconfigurable hardware device implementing a separate application; and

calculating the layout section includes calculating the layout section within the application-tree for fitting the fragment circuitry into the unoccupied logic-sector around the separate application while implementing the separate application.

7. The method as claimed in claim 6 wherein:

determining the system table includes determining the system table having time slots for scheduling the fragment circuitry; and

further comprising:

adjusting the time slots for rescheduling the fragment circuitry based on a determined priority.

8. The method as claimed in claim 6 further comprising:

forming a signal buffer for managing data required to implement the application;

adjusting the system table for implementing the signal buffer to produce a pipe-result; and

clearing the signal buffer according to the system table.

9. The method as claimed in claim 6 wherein:

receiving an outer-optimization through an interface-session for optimizing a combination of a further circuitry at the coupled kernel instance and the fragment circuitry; and

adjusting the system table according to the optimization result for optimizing the combination of the further circuitry and the fragment circuitry.

10. The method as claimed in claim 6 further comprising:

establishing an interface-session for accessing resources coupled to a coupled kernel instance;

calculating an optimization result for optimizing a combination of the fragment circuitry and a further circuitry coupled to the coupled kernel instance; and

sending the optimization result through the interface-session for optimizing the further circuitry.

11. The method as claimed in claim 6 further comprising:

determining a branch statistic corresponding to the fragment circuitry for characterizing a usage of the fragment circuitry; and

calculating a determined priority based on the branch statistic.

12. The method as claimed in claim 6 further comprising:

calculating an optimization result for optimizing the reconfigurable hardware device based on usage to implement the application and the separate application; and

adjusting the system table according to the optimization result for rearranging machines within the reconfigurable hardware device to optimize the application and the separate application.

13. The method as claimed in claim 6 further comprising decimating the fragment circuitry for maximizing a capacity of the reconfigurable hardware device based on usage.

14. The method as claimed in claim 6 wherein:

determining the system table includes determining the system table having time slots for scheduling the fragment circuitry; and

further comprising:

adjusting the time slots for removing a value corresponding to the fragment circuitry based on usage.

15. The method as claimed in claim 6 further comprising:

forming a signal buffer for managing data required by the reconfigurable hardware device;

setting an application-space within the signal buffer for managing data required by the pipeline; and

adjusting the application-space.

16. A computing system comprising:

a user interface unit for receiving an application-tree for instantiating an application in a reconfigurable hardware device;

a resource manager, coupled to the user interface unit, operating a kernel unit for determining an unoccupied logic-sector within a reconfigurable hardware device;

a layout calculator, coupled to the user interface unit, for calculating a layout section from the application-tree according to the unoccupied logic-sector for instantiating a fragment circuitry corresponding to the layout section; and

a database-manager, coupled to the user interface unit, for determining a system table for connecting the fragment circuitry to other portions of the application to form the application having the fragment circuitry including scheduling a time slot in a machine reservation for incorporating the fragment circuitry instantiated until the time slot.

17. The system as claimed in claim 16 wherein:

the user interface unit is for receiving an application-descriptor for instantiating the application;

the resource manager is for calculating a further layout section having an instantiation condition based on the application-descriptor for implementing a different portion of the application; and

further comprising:

an application manager, coupled to the user interface unit, for forming a further circuitry for implementing the different portion of the application when the instantiation condition has been met.

18. The system as claimed in claim 16 wherein:

the resource manager is for determining a further-available logic-sector for implementing a different portion of the application through a coupled kernel instance;

the layout calculator is for calculating a further layout section having a circuit characteristic for instantiating a further circuitry corresponding to the further layout section;

the database-manager is for adjusting the system table for forming the application having the further circuitry; and

further comprising:

an inter-cluster communication unit, coupled to the user interface unit, for sending the further layout section for forming the further circuitry through the coupled kernel instance to implement the different portion of the application.

19. The system as claimed in claim 16 wherein:

the resource manager is for calculating a further-available logic-sector for reallocating contents within the reconfigurable hardware device; and

the database-manager is for adjusting the system table for relocating the fragment circuitry into the further-available logic-sector.

20. The system as claimed in claim 16 further comprising:

the layout calculator is for recalculating the fragment circuitry for rearranging the application; and

the database-manager is for adjusting the system table for implementing the fragment circuitry after the recalculating.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2012
From: ZIEVERS, PETER J.
To: XCELEMOR, INC.
Reel/Frame 028161/0497 →
Continuity (2)
Provisional Application 61483523 · May 6, 2011
Related Publication 20120284502A1 · Nov 8, 2012