IP Library › Granted Patent US 8,761,237
Granted Patent B2
US 8,761,237 · App. 13/288,096 · Granted Jun 24, 2014

Low nonlinear distortion variable gain amplifier

Inventors: Pervez M. Aziz (Dallas, TX); Hiroshi Kimura (San Jose, CA)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,761,237
App. No.
13/288,096
Granted
Jun 24, 2014
Kind
B2
Abstract

A variable gain amplifier (VGA) useful in a receiver that recovers transmitted digital signals. A first amplifier in the VGA has a first gain, an input coupled to an input of the VGA, and an output coupled to a load. A second amplifier in the VGA has a second gain, an input coupled to the input of the VGA, and an output coupled to the load. In a first mode of operation, the first gain is substantially zero and the second gain ranges between a maximum gain and a fraction of the maximum gain. In a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain and the fraction of the maximum gain, and an algebraic sum of the first gain and second gain is no greater than the maximum gain to reduce non-linear distortion at low VGA gain.

Claims (53)

1. In an integrated circuit, an equalizer having an input and an output, the equalizer comprising:

a load coupled to the output of the equalizer;

a first amplifier having a first gain, an input coupled to the input of the equalizer, and an output coupled to the load; and

a second amplifier having a second gain, an input coupled to the input of the equalizer, and an output coupled to the load;

wherein, in a first mode of operation the second gain is substantially zero and the first gain ranges between a maximum gain Km and a gain breakpoint Kb,

wherein in a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain Km and the gain breakpoint Kb, wherein the combined gain of the first and second amplifiers applied to the load in the first mode is between Kb and Km and the combined gain in the second mode is between 0 and Kb, and

wherein the gain breakpoint Kb is less than the maximum gain and greater than zero.

2. The integrated circuit of claim 1 , wherein the gain breakpoint Kb is approximately one-half the maximum gain Km.

3. The integrated circuit of claim 1 , wherein the output of the second amplifier is coupled to the load in a phase opposite to that of the first amplifier.

4. The integrated circuit of claim 1 , wherein the first and second amplifiers each have a differential amplifier responsive to respective first and second tail currents that controls the respective gain of the first and second amplifiers.

5. The integrated circuit of claim 4 , wherein the tail currents are digitally controlled.

6. The integrated circuit of claim 1 , wherein the load includes a resistor.

7. The integrated circuit of claim 6 , wherein the first and second gains are first and second transconductances of the first and second amplifiers, respectively, and the maximum gain is a maximum transconductance of the second amplifier, and the variable gain amplifier has a voltage gain determined by an algebraic combination of the transconductance of the first and second amplifiers multiplied by the impedance of the load.

8. The integrated circuit of claim 1 , wherein the equalizer has differential inputs and outputs, the first and second amplifiers are differential amplifiers, and the load includes two resistors coupled between a voltage supply line and corresponding conductors of the differential output.

9. A receiver having an analog equalizer, the equalizer comprising:

an input and an output;

a first filter coupled between the input and the output of the equalizer;

a second filter coupled between the input of the equalizer and a node;

a first amplifier having a first gain, an input coupled to the node, and an output coupled to the output of the equalizer; and

a second amplifier having second gain, an input coupled to the node, and an output coupled to the output of the equalizer;

wherein, in a first mode of operation the second gain is substantially zero and the first gain ranges between a maximum gain Km and a gain breakpoint Kb,

wherein in a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain Km and the gain breakpoint Kb,

wherein the combined gain of the first and second amplifiers applied to a load in the first mode is between Kb and Km and the combined gain in the second mode is between 0 and Kb, and

wherein the gain breakpoint Kb is less than the maximum gain Km and greater than zero.

10. The receiver of claim 9 , wherein the gain breakpoint Kb is substantially one-half the maximum gain Km.

11. The receiver of claim 9 , wherein the output of the second amplifier is coupled to the load in a phase opposite to that of the first amplifier.

12. The receiver of claim 9 , wherein the first and second gains are transconductances of the first and second amplifiers, respectively, and the first and second amplifiers each have a differential amplifier responsive to respective first and second tail currents that control the transconductance of the first and second amplifiers, respectively.

13. The receiver of claim 12 , wherein the tail currents are digitally controlled.

14. The receiver of claim 9 , wherein the load includes a resistor.

15. The receiver of claim 9 , wherein the first filter has a unity transfer function and the second filter has a high-pass transfer function.

16. The receiver of claim 9 , wherein the first filter has a low-pass transfer function and the second filter has a high-pass transfer function.

17. The receiver of claim 9 , further comprising an adjustable gain amplifier disposes between the input of the equalizer and the first and second filters.

18. The receiver of claim 9 wherein the equalizer has differential inputs and outputs, the first and second variable transconductance amplifiers are differential amplifiers, and the load includes two resistors coupled between a voltage supply line and corresponding conductors of the differential output.

19. A method of amplifying a signal in an equalizer, the method comprising the steps of:

amplifying the signal using a first amplifier having a first gain;

amplifying the signal using a second amplifier having second gain; and

subtracting the amplified signal from the second amplifier from the amplified signal from the first amplifier and providing an output;

wherein in a first mode of operation the second gain is substantially zero and the first gain ranges between a maximum gain Km and a gain breakpoint Kb, and in a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain Km and the gain breakpoint Kb, and the gain breakpoint Kb is less than the maximum gain Km and greater than zero;

wherein the output is provided to a load.

20. The method of claim 19 , wherein the gain breakpoint Kb is approximately one-half the maximum gain Km.

21. The method of claim 19 , wherein the first and second gains are first and second transconductances of the first and second amplifiers, respectively, and the first and second amplifiers each have a differential amplifier responsive to respective first and second tail currents that control the transconductance of the first and second amplifiers, respectively.

22. The method of claim 21 , wherein the tail currents are digitally controlled.

23. A receiver having an equalizer with an input and an output, the equalizer comprising:

a resistive load coupled to the output of the equalizer;

a first variable transconductance amplifier having a first transconductance, an input coupled to the input of the equalizer, and an output coupled to the output of the equalizer; and

a second variable transconductance amplifier having a second transconductance, an input coupled to the input of the equalizer, and an output coupled to the output of the equalizer in a phase opposite to that of the first variable transconductance amplifier;

wherein, in a first mode of operation the second transconductance is substantially zero and the first transconductance ranges between a maximum transconductance Km and a transconductance breakpoint Kb, and in a second mode of operation the first transconductance is substantially equal to the maximum transconductance and the second transconductance ranges between the maximum transconductance Km and the transconductance breakpoint Kb, wherein the combined gain of the first and second transconductance amplifier applied to the load in the first mode is between Kb and Km and the combined gain in the second mode is between 0 and Kb and, and the transconductance breakpoint Kb is sufficient to assure that no substantial nonlinear distortion occurs by the equalizer.

24. The receiver of claim 23 , wherein the transconductance breakpoint Kb is substantially one-half the maximum transconductance Km.

25. The receiver of claim 23 , wherein the first and second variable transconductance amplifiers each have a differential amplifier responsive to the respective first and second tail currents that control the respective transconductance of the first and second variable transconductance amplifiers.

26. The receiver of claim 23 , wherein the tail currents are digitally controlled.

27. The integrated circuit of claim 1 wherein the gain breakpoint Kb is greater than a minimum gain, the minimum gain being sufficient to assure that no substantial nonlinear distortion occurs by the equalizer.

28. The receiver of claim 9 wherein the gain breakpoint Kb is greater than a minimum gain, the minimum gain being sufficient to assure that no substantial nonlinear distortion occurs by the equalizer.

29. The method of claim 19 , wherein the gain breakpoint Kb is greater than a minimum gain, the minimum gain being sufficient to assure that no substantial nonlinear distortion occurs in the subtracted amplified signals.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2011
From: AZIZ, PERVEZ M.; KIMURA, HIROSHI
To: LSI CORPORATION
Reel/Frame 027166/0984 →
Continuity (1)
Related Publication 20130114665A1 · May 9, 2013