IP Library Granted Patent US 8,768,990
Granted Patent B2
US 8,768,990 · App. 13/294,332 · Granted Jul 1, 2014

Reconfigurable cyclic shifter arrangement

Inventors: Kiran Gunnam (San Jose, CA); Madhusudan Kalluri (Sunnyvale, CA)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,768,990
App. No.
13/294,332
Granted
Jul 1, 2014
Kind
B2
Abstract

In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4×4 cyclic shifters to cyclically shift four sets of four input values. In a second mode, the reconfigurable cyclic shifter is configured as two 8×8 cyclic shifters to cyclically shift two sets of eight input values. In a third mode, the reconfigurable cyclic shifter is configured as one 16×16 cyclic shifter to cyclically shift one set of 16 input values. Because the first and second reconfigurable cyclic shifters are independently configurable, there are nine different configurations of the reconfigurable cyclic shifter arrangement.

Claims (59)

1. An apparatus comprising a reconfigurable cyclic shifter arrangement, the reconfigurable cyclic shifter arrangement comprising:

a first reconfigurable cyclic shifter adapted to cyclically shift N input values, N≧4, to generate a first set of N output values;

a second reconfigurable cyclic shifter adapted to cyclically shift the first set of N output values to generate a second set of N output values; and

a controller adapted to selectively configure (i) the first reconfigurable cyclic shifter to operate in any one of at least first and second operating modes and (ii) the second reconfigurable cyclic shifter to operate in any one of the at least first and second operating modes, independent of the configuration of the first reconfigurable cyclic shifter, wherein:

a reconfigurable cyclic shifter configured in the first operating mode operates as a first set of cyclic shifters, the first set comprising one or more independent cyclic shifters, to independently cyclically shift one or more different subsets of N values; and

a reconfigurable cyclic shifter configured in the second operating mode operates as a second set of cyclic shifters, the second set comprising two or more independent cyclic shifters, to independently cyclically shift two or more different subsets of N values, wherein the number of independent cyclic shifters in the second set is greater than the number of independent cyclic shifters in the first set.

2. The apparatus of claim 1 , wherein:

in a first configuration of the reconfigurable cyclic shifter arrangement, the first and second reconfigurable cyclic shifters are both configured to operate in the first operating mode;

in a second configuration of the reconfigurable cyclic shifter arrangement, the first and second reconfigurable cyclic shifters are both configured to operate in the second operating mode;

in a third configuration of the reconfigurable cyclic shifter arrangement, the first reconfigurable cyclic shifter is configured to operate in the first mode and the second reconfigurable cyclic shifter is configured to operate in the second mode; and

in a fourth configuration of the reconfigurable cyclic shifter arrangement, the first reconfigurable cyclic shifter is configured to operate in the second mode and the second reconfigurable cyclic shifter is configured to operate in the first mode.

3. The apparatus of claim 2 , wherein the reconfigurable cyclic shifter arrangement is configured in either the third configuration or the fourth configuration.

4. The apparatus of claim 1 , further comprising:

a first multiplexer adapted to selectively output one of the first and second sets of N output values to a first data path; and

a second multiplexer adapted to selectively output a remaining one of the first and second sets of N output values to a second data path, different from the first data path.

5. The apparatus of claim 1 , wherein each of the first and second reconfigurable cyclic shifters comprises:

at least one pre-multiplexer stage comprising a plurality of multiplexers; and

at least two independent cyclic shifters, wherein:

the at least one pre-multiplexer stage is adapted to (i) receive N values and (ii) selectively output a different subset of the N values to each of the at least two independent cyclic shifters; and

each of the at least two independent cyclic shifters is adapted to independently cyclically shift the corresponding different subset of the N values.

6. The apparatus of claim 5 , wherein each of the multiplexers is a (2×1) multiplexer.

7. The apparatus of claim 5 , wherein each of the first and second reconfigurable cyclic shifters comprises a plurality of pre-multiplexer stages.

8. The apparatus of claim 1 , wherein the apparatus comprises a low-density parity-check (LDPC) decoder comprising the reconfigurable cyclic shifter arrangement.

9. The apparatus of claim 8 , wherein the LDPC decoder is adapted to decode codewords encoded based on an H-matrix having two or more different circulant sizes.

10. The apparatus of claim 1 , wherein:

the first set of N output values is shifted relative to the N input values; and

the second set of N output values is unshifted relative to the N input values.

11. The apparatus of claim 1 , wherein the apparatus is an integrated circuit.

12. An apparatus comprising a reconfigurable cyclic shifter arrangement, the reconfigurable cyclic shifter arrangement comprising:

first shifting means for cyclically shifting N input values, N>≧4, to generate a first set of N output values;

second shifting means for cyclically shifting the first set of N output values to generate a second set of N output values; and

control means for selectively configuring (i) the first means to operate in any one of at least first and second operating modes and (ii) the second means to operate in any one of the at least first and second operating modes, independent of the configuration of the first means, wherein:

in the first operating mode, the shifting means operates as a first set of cyclic shifters, the first set comprising one or more independent cyclic shifters, to independently cyclically shift one or more different subsets of N values; and

in the second operating mode, the shifting means operates as a second set of cyclic shifters, the second set comprising two or more independent cyclic shifters, to independently cyclically shift two or more different subsets of N values, wherein the number of independent cyclic shifters in the second set is greater than the number of independent cyclic shifters in the first set.

13. A machine-implemented method, the method comprising:

cyclically shifting N input values, N≧4, using a first reconfigurable cyclic shifter to generate a first set of N output values;

cyclically shifting the first set of N output values using a second reconfigurable cyclic shifter to generate a second set of N output values; and

selectively configuring (i) the first reconfigurable cyclic shifter to operate in any one of at least first and second operating modes and (ii) the second reconfigurable cyclic shifter to operate in any one of the at least first and second operating modes, independent of the configuration of the first reconfigurable cyclic shifter, wherein:

a reconfigurable cyclic shifter configured in the first operating mode operates as a first set of cyclic shifters, the first set comprising one or more independent cyclic shifters, to independently cyclically shift one or more different subsets of N values; and

a reconfigurable cyclic shifter configured in the second operating mode operates as a second set of cyclic shifters, the second set comprising two or more independent cyclic shifters, to independently cyclically shift two or more different subsets of N values, wherein the number of independent cyclic shifters in the second set is greater than the number of independent cyclic shifters in the first set.

14. The method of claim 13 , wherein:

in a first configuration, the first and second reconfigurable cyclic shifters are both configured to operate in the first operating mode;

in a second configuration, the first and second reconfigurable cyclic shifters are both configured to operate in the second operating mode;

in a third configuration, the first reconfigurable cyclic shifter is configured to operate in the first mode and the second reconfigurable cyclic shifter is configured to operate in the second mode; and

in a fourth configuration, the first reconfigurable cyclic shifter is configured to operate in the second mode and the second reconfigurable cyclic shifter is configured to operate in the first mode.

15. The method of claim 14 , wherein the reconfigurable cyclic shifter arrangement is configured in either the third configuration or the fourth configuration.

16. The method of claim 13 , further comprising:

selectively outputting one of the first and second sets of N output values to a first data path; and

selectively outputting a remaining one of the first and second sets of N output values to a second data path, different from the first data path.

17. The method of claim 13 , wherein each of the first and second reconfigurable cyclic shifters comprises:

at least one pre-multiplexer stage comprising a plurality of multiplexers; and

at least two independent cyclic shifters, wherein:

the at least one pre-multiplexer stage is adapted to (i) receive N values and (ii) selectively output a different subset of the N values to each of the at least two independent cyclic shifters; and

each of the at least two independent cyclic shifters is adapted to independently cyclically shift the corresponding different subset of the N values.

18. The method of claim 13 , wherein the method comprises performing low-density parity-check (LDPC) decoding of a codeword, wherein the cyclic shifting is a step performed in the LDPC decoding.

19. The method of claim 18 , wherein the LDPC decoding comprises decoding codewords encoded based on an H-matrix having two or more different circulant sizes.

20. The method of claim 13 , comprising:

shifting the first set of N output values relative to the N input values; and

shifting the second set of N output values relative to the N input values.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2011
From: GUNNAM, KIRAN; KALLURI, MADHUSUDAN
To: LSI CORPORATION
Reel/Frame 027214/0332 →
Continuity (1)
Related Publication 20130124590A1 · May 16, 2013