IP Library › Granted Patent US 8,772,857
Granted Patent B2
US 8,772,857 · App. 13/221,380 · Granted Jul 8, 2014

Vertical memory devices and methods of manufacturing the same

Inventors: Byeong-In Choe (Yongin-si, KR); Jae-Hoon Jang (Seongnam-si, KR); Sun-Il Shim (Songpa-gu, KR); Han-Soo Kim (Suwon-si, KR); Jin-Man Han (Seongnam-si, KR)
Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 8,772,857
App. No.
13/221,380
Granted
Jul 8, 2014
Kind
B2
Abstract

A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.

Claims (58)

1. A vertical memory device, comprising:

a channel extending in a first direction substantially perpendicular to a top surface of a substrate, a thickness of the channel varying according to height;

at least one ground selection line (GSL), a plurality of word lines and at least one string selection line (SSL) spaced apart from each other on a sidewall of the channel in the first direction,

the at least one GSL, the plurality of word lines, and the at least one SSL defining an opening through which the channel extends in the first direction,

the opening having a width that does not vary substantially along the first direction,

the channel including an outer surface that extends in the first direction from the at least one GSL to the at least one SSL,

the outer surface of the channel having a perimeter that substantially does not vary according to height along the first direction; and

a tunnel insulation layer pattern, a charge trapping layer pattern and a blocking layer pattern sequentially stacked in a second direction substantially perpendicular to the sidewall of the channel, the tunnel insulation layer pattern, the charge trapping layer pattern and the blocking layer pattern between the sidewall of the channel and each of the GSL, the word lines, and the SSL.

2. The device of claim 1 , wherein the channel includes a lower portion and an upper portion, a thickness of the lower portion greater than a thickness of the upper portion.

3. The device of claim 2 , wherein a height of the lower portion is less than a height of the SSL.

4. The device of claim 1 , wherein the channel includes a lower portion, a central portion and an upper portion, a thickness of the lower portion and a thickness of the upper portion each less than a thickness of the central portion.

5. The device of claim 4 , wherein a height of the central portion is less than a height of the SSL and greater than a height of the GSL.

6. The device of claim 1 , further comprising:

a dummy word line on the sidewall of the channel between at least two of the plurality of word lines,

wherein the channel includes a lower portion of a first thickness, a first central portion of a second thickness, a second central portion of a third thickness, and an upper portion of a fourth thickness, each of the second and fourth thicknesses being less than each of the first and third thicknesses.

7. The device of claim 6 , wherein:

the first central portion is at a same height as the dummy word line, and

the upper portion is at a same height as the SSL.

8. The device of claim 1 , further comprising:

a dummy word line on the sidewall of the channel between at least two of the plurality of word lines,

wherein the channel includes a lower portion of a first thickness, a first central portion of a second thickness, a second central portion of a third thickness, a third central portion of a fourth thickness, and an upper portion of a fifth thickness, each of the first, third and fifth thicknesses being less than each of the second and fourth thicknesses.

9. The device of claim 8 , wherein:

the lower portion is at a same height as the GSL,

the second central portion is at a same height as the dummy word line, and

the upper portion is at a same height as the SSL.

10. The device of claim 1 , wherein the channel is a plurality of cup shaped channels spaced apart in a second direction substantially parallel to the top surface of the substrate.

11. The device of claim 1 , wherein the channel is a plurality of linearly shaped channels spaced apart in a second direction substantially parallel to the top surface of the substrate.

12. The device of claim 1 , further comprising:

a common source line (CSL) extending in a third direction substantially perpendicular to the second direction at an upper portion of the substrate; and

a bit line extending in the second direction and electrically connected to the channel.

13. A method of manufacturing a vertical memory device, comprising:

forming at least one ground selection line (GSL), a plurality of word lines and at least one string selection line (SSL) spaced apart in a first direction on a substrate,

the at least one GSL, the plurality of word lines, and the at least one SSL defining an opening having a width that does not substantially vary along the first direction;

forming a channel in the opening on the substrate, the channel having a thickness that varies according to a height,

the channel extending in the first direction substantially perpendicular to the top surface of the substrate,

the channel including an outer surface that extends in the first direction from the at least one GSL to the at least one SSL,

the outer surface of the channel having a perimeter that substantially does not vary according to height along the first direction; and

forming a tunnel insulation layer pattern, a charge trapping layer pattern, and a blocking layer pattern sequentially stacked in a second direction substantially perpendicular to the sidewall of the channel and each of the GSL, the plurality of word lines, and the SSL.

14. The method of claim 13 , wherein the forming a channel includes forming a lower portion of the channel to a first thickness and forming an upper portion of the channel to a second thickness less than the first thickness, the lower portion being formed to a height less than a height of the SSL.

15. A vertical memory device, comprising:

a ground selection line (GSL);

a word line (WL) on the GSL;

a string selection line (SSL) on the WL;

a channel of varying thickness crossing the GSL, WL and SSL,

the channel having an outer surface that extends in a first direction from the GSL to the SSL,

the outer surface of the channel having a perimeter that substantially does not vary according to height along the first direction; and

a tunnel insulation layer pattern, a charge trapping layer pattern and a blocking layer pattern sequentially stacked,

the tunnel insulation layer pattern, the charge trapping layer pattern and the blocking layer pattern extending between a sidewall of the channel and each of the GSL, the plurality of word lines, and the SSL.

16. The device of claim 15 , wherein a thickness of the channel is greatest adjacent to the WL.

17. The device of claim 16 , further comprising:

an insulation layer at least partially surrounded by the channel and including at least two different insulating materials.

18. The device of claim 15 , further comprising:

a dummy word line (DWL) on the WL, a thickness of the channel adjacent to the DWL less than a thickness of the channel adjacent to the WL,

wherein a thickness of the channel adjacent to at least one of the GSL and SSL is less than the thickness of the channel adjacent to the WL.

19. The device of claim 18 , wherein:

the thickness of the channel adjacent to at least one of the GSL and the SSL is the thickness of the channel adjacent to the GSL;

the thickness of the channel adjacent to the WL is greater than a thickness of the channel adjacent to the SSL; and

the thickness of the channel adjacent to the GSL is different from a thickness of the channel adjacent to the SSL.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2011
From: CHOE, BYEONG-IN; JANG, JAE-HOON; SHIM, SUN-IL; KIM, HAN-SOO; HAN, JIN-MAN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 026836/0660 →
Priority Claims (1)
KR 10-2010-0102715 · Oct 21, 2010 · national
Continuity (1)
Related Publication 20120098048A1 · Apr 26, 2012