IP Library Granted Patent US 8,772,868
Granted Patent B2
US 8,772,868 · App. 13/095,670 · Granted Jul 8, 2014

Superjunction structures for power devices and methods of manufacture

Inventors: Joseph A. Yedinak (Mountain Top, PA); Mark L. Rinehimer (Mountain Top, PA); Praveen Muraleedharan Shenoy (Kochi, ID); Hamza Yilmaz (Saratoga, CA); James Pan (Costa Mesa, CA); Rodney S. Ridley, Sr. (Quakertown, PA)
Assignee: Fairchild Semiconductor Corporation
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Quick Facts
Patent No.
US 8,772,868
App. No.
13/095,670
Granted
Jul 8, 2014
Kind
B2
Abstract

A power device includes a semiconductor substrate having a plurality of alternately arranged pillars of first and second conductivity types. At least one of the plurality of pillars of second conductivity type includes a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench, a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type.

Claims (69)

1. A power device comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer of the first conductivity type disposed on the semiconductor substrate;

a first trench disposed in the epitaxial layer of the first conductivity type;

a second trench disposed in the epitaxial layer of the first conductivity type; and

a mesa disposed between the first trench and the second trench, the mesa defining a pillar of the first conductivity type from the epitaxial layer of the first conductivity type;

a body region of a second conductivity type disposed in the epitaxial layer of the first conductivity type;

a source region of the first conductivity type disposed in the body region;

a gate electrode disposed on the body region and disposed on at least a portion of the source region, the gate electrode being insulated from the body region and the source region; and

a source metal layer in electrical contact with the source region,

the first trench including a first pillar of the second conductivity type,

the second trench including a second pillar of the second conductivity type, the second pillar of the second conductivity type including:

a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench,

a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and

an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type,

the first pillar of the second conductivity type and the second pillar of the second conductivity type forming pillars of alternating conductivity type with the pillar of the first conductivity type.

2. The power device of claim 1 , wherein the epitaxial layer of the first conductivity type includes a plurality of epitaxial layers of the first conductivity type.

3. The power device of claim 1 , wherein the insulating material layer includes a thermal oxide.

4. The power device of claim 1 , wherein a doping concentration of the second epitaxial layer of the second conductivity type has a lower doping concentration than a doping concentration of the first epitaxial layer of the second conductivity type.

5. A power device comprising:

a first N-type epitaxial layer disposed on a substrate;

a second N-type epitaxial layer disposed on the first N-type epitaxial layer;

a first trench extending through the second N-type epitaxial layer and terminating within the first N-type epitaxial layer;

a second trench extending through the second N-type epitaxial layer and terminating within the first N-type epitaxial layer; and

a mesa disposed between the first trench and the second trench, the mesa defining an N-type pillar from the first N-type epitaxial layer and the second N-type epitaxial layer,

the first trench including a first P-type pillar,

the second trench including a second P-type pillar,

the first P-type pillar and the second P-type pillar forming pillars of alternating conductivity type with the N-type pillar,

each P-type pillar including:

a first trench epitaxial layer disposed on a trench sidewall and a trench bottom surface; and

a second trench epitaxial layer disposed on the first trench epitaxial layer, the first trench epitaxial layer including an N-type epitaxial layer having a doping concentration that is lower than a doping concentration of the second trench epitaxial layer, the second trench epitaxial layer including a P-type epitaxial layer.

6. The power device of claim 5 , wherein each P-type pillar further includes a conductive material layer disposed on the second trench epitaxial layer.

7. The power device of claim 6 , wherein:

the second trench epitaxial layer has a doping concentration that is higher than a doping concentration of the first trench epitaxial layer; and

the conductive material layer has a doping concentration that is higher than the doping concentration of the second trench epitaxial layer.

8. The power device of claim 6 , wherein the conductive material layer includes an N-type layer that has a doping concentration that is lower than a doping concentration of the second trench epitaxial layer.

9. The power device of claim 6 , wherein the conductive material layer includes an intrinsic epitaxial layer.

10. The power device of claim 6 , wherein the conductive material layer includes polysilicon.

11. The power device of claim 5 , wherein the first N-type epitaxial layer includes intrinsic silicon.

12. The power device of claim 5 , further comprising:

a first P-enrichment region disposed at a bottom of the first P-type pillar and

a second P-enrichment region disposed at a bottom of the second P-type pillar.

13. The power device of claim 5 , wherein the N-type pillar includes an upper N-region, a middle N-region and a lower N-region, the upper N-region has a doping concentration that is lower than a doping concentration of the middle N-region, and the doping concentration of the middle N-region is lower than a doping concentration of the lower N-region.

14. The power device of claim 5 , further comprising:

a P-type body region disposed in the second N-type epitaxial layer;

an N-type source region disposed in the body region;

a gate electrode disposed on the body region and disposed on at least a portion of the N-type source region, the gate electrode being insulated from the body region and the source region; and

a source metal layer in electrical contact with the source region.

15. The power device of claim 14 , wherein the source metal layer is in electrical contact with the first P-type pillar and the second P-type pillar.

16. A power device comprising:

a first N-type epitaxial layer disposed on a substrate;

a second N-type epitaxial layer disposed on the first N-type epitaxial layer;

a first trench extending through the second N-type epitaxial layer and terminating within the first N-type epitaxial layer;

a second trench extending through the second N-type epitaxial layer and terminating within the first N-type epitaxial layer; and

a mesa disposed between the first trench and the second trench, the mesa defining an N-type pillar from the first N-type epitaxial layer and the second N-type epitaxial layer,

the first trench including a first P-type pillar,

the second trench including a second P-type pillar,

the first P-type pillar and the second P-type pillar forming pillars of alternating conductivity type with the N-type pillar, and

the N-type pillar including an upper N-region, a middle N-region and a lower N-region, the upper N-region having a doping concentration that is lower than a doping concentration of the middle N-region, and the doping concentration of the middle N-region being lower than a doping concentration of the lower N-region.

17. The power device of claim 16 , wherein the first N-type epitaxial layer includes intrinsic silicon.

18. The power device of claim 16 , further comprising:

a first P-enrichment region disposed at a bottom of the first P-type pillar and

a second P-enrichment region disposed at a bottom of the second P-type pillar.

19. The power device of claim 16 , further comprising:

a P-type body region disposed in the second N-type epitaxial layer;

an N-type source region disposed in the body region;

a gate electrode disposed on the body region and disposed on at least a portion of the N-type source region, the gate electrode being insulated from the body region and the source region; and

a source metal layer in electrical contact with the source region.

20. The power device of claim 19 , wherein the source metal layer is in electrical contact with the first P-type pillar and the second P-type pillar.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2012
From: YEDINAK, JOSEPH A.; REXER, CHRISTOPHER L.; RINEHIMER, MARK L.; SHENOY, PRAVEEN MURALEEDHARAN; LEE, JAEGIL; YILMAZ, HAMZA; YUN, CHONGMAN; REICHL, DWAYNE S.; PAN, JAMES; RIDLEY, RODNEY S., SR.; HEIDENREICH, HAROLD
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 027955/0098 →
Continuity (1)
Related Publication 20120273875A1 · Nov 1, 2012