Interconnection and assembly of three-dimensional chip packages
In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.
1. A chip package, comprising:
a group of semiconductor dies arranged in a plank stack in an x direction, wherein a plane of a given semiconductor die is defined by a z direction and a y direction, wherein the semiconductor dies include first electrical pads proximate to edges of the semiconductor dies, wherein the edges of the semiconductor dies define a face of the plank stack, wherein surfaces of the semiconductor dies are defined by the z direction and the y direction, and wherein the surfaces of the semiconductor dies include negative features recessed below the surfaces;
positive features mechanically coupled to the negative features on adjacent semiconductor dies, thereby aligning the semiconductor dies in the plank stack; and
an interposer plate electrically coupled to the semiconductor dies along the x direction, wherein a plane of the interposer plate is defined by the x direction and the y direction;
wherein the electrical coupling to the semiconductor dies is between the first electrical pads, second electrical pads proximate to a surface of the interposer plate along the x direction, and an intervening conductive material between the first electrical pads and the second electrical pads.
2. The chip package of claim 1 , wherein a first electrical pad on a given semiconductor die is included in a second negative feature recessed below one of the surfaces of the given semiconductor die.
3. The chip package of claim 2 , wherein the second negative feature is included in a dicing lane of the given semiconductor die.
4. The chip package of claim 1 , wherein the intervening conductive material includes solder balls.
5. The chip package of claim 4 , wherein the edges of the semiconductor dies are surrounded by the solder balls.
6. The chip package of claim 1 , wherein the intervening conductive material includes mechanically compliant electrical connectors.
7. The chip package of claim 6 , wherein the mechanically compliant electrical connectors include an array of spring connectors.
8. The chip package of claim 7 , wherein surfaces of a given semiconductor die are positioned between and mechanically coupled to at least a pair of spring connectors in the array of spring connectors.
9. The chip package of claim 1 , wherein a first electrical pad on a given semiconductor die is electrically coupled to an additional pad on the given semiconductor die by an electrical signal line.
10. The chip package of claim 1 , further comprising:
a mechanical-alignment plate; and
mechanical-alignment components, wherein the plank stack is mechanically coupled to the mechanical-alignment plate by the mechanical-alignment components, thereby facilitating alignment of the semiconductor dies in the plank stack; and
wherein the mechanical-alignment plate is mechanically coupled to the plank stack on an opposite face of the plank stack from the interposer plate.
11. The chip package of claim 10 , wherein the mechanical-alignment components include at least one of: spheres, clamps and pins.
12. The chip package of claim 1 , wherein the semiconductor dies include third electrical pads proximate to the edges of the semiconductor dies along the y direction;
wherein the interposer plate is further electrically coupled to the semiconductor dies along the y direction; and
wherein the electrical coupling to the semiconductor dies is between the third electrical pads, fourth electrical pads proximate to the surface of the interposer plate along the y direction, and the intervening conductive material between the third electrical pads and the fourth electrical pads.
13. The chip package of claim 1 , wherein the second electrical pads include one of: discrete pads and a continuous electrical signal line on the interposer plate.
14. The chip package of claim 1 , further comprising mechanical-alignment components mechanically coupled to the edges of the semiconductor dies and the interposer plate.
15. The chip package of claim 1 , wherein the semiconductor dies are mechanically coupled by adhesive layers in spaces between the semiconductor dies; and
wherein the adhesive layers are recessed from the first electrical pads in the spaces between pairs of semiconductor dies.
16. A system, comprising a chip package, wherein the chip package includes:
a processor;
a memory;
wherein the memory comprises a group of semiconductor dies arranged in a plank stack in an x direction, wherein a plane of a given semiconductor die is defined by a z direction and a y direction, wherein the semiconductor dies include first electrical pads proximate to edges of the semiconductor dies, wherein the edges of the semiconductor dies define a face of the plank stack, wherein surfaces of the semiconductor dies are defined by the z direction and the y direction, and wherein the surfaces of the semiconductor dies include negative features recessed below the surfaces;
positive features mechanically coupled to the negative features on adjacent semiconductor dies, thereby aligning the semiconductor dies in the plank stack; and
an interposer plate electrically coupled to the semiconductor dies along the x direction, wherein a plane of the interposer plate is defined by the x direction and the y direction;
wherein the electrical coupling to the semiconductor dies is between the first electrical pads, second electrical pads proximate to a surface of the interposer plate along the x direction, and an intervening conductive material between the first electrical pads and the second electrical pads.
17. The system of claim 16 , wherein a first electrical pad on a given semiconductor die is included in the second negative feature recessed below one of the surfaces of the given semiconductor die.
18. The system of claim 17 , wherein the other negative feature is included in a dicing lane of the given semiconductor die.
19. The system of claim 16 , further comprising:
a mechanical-alignment plate; and
mechanical-alignment components, wherein the plank stack is mechanically coupled to the mechanical-alignment plate by the mechanical-alignment components, thereby facilitating alignment of the semiconductor dies in the plank stack; and
wherein the mechanical-alignment plate is mechanically coupled to the plank stack on an opposite face of the plank stack from the interposer plate.
20. A method for fabricating a plank stack of semiconductor dies in an x direction, wherein the method comprises:
stacking the semiconductor dies along the x direction into the plank stack, wherein a plane of a given semiconductor die is defined by a z direction and a y direction, wherein the semiconductor dies include first electrical pads proximate to edges of the semiconductor dies, wherein the edges of the semiconductor dies define a face of the plank stack, wherein surfaces of the semiconductor dies are defined by the z direction and the y direction, and wherein the surfaces of the semiconductor dies include negative features recessed below the surfaces;
while stacking the semiconductor dies, aligning the semiconductor dies in the plank stack by mechanically coupling positive features to the negative features on adjacent semiconductor dies; and
electrically coupling an interposer plate to the semiconductor dies along the x direction, wherein a plane of the interposer plate is defined by the x direction and the y direction;
wherein the electrical coupling to the semiconductor dies is between the first electrical pads, second electrical pads proximate to a surface of the interposer plate along the x direction, and an intervening conductive material between the first electrical pads and the second electrical pads.