IP Library › Granted Patent US 8,773,583
Granted Patent B2
US 8,773,583 · App. 13/086,830 · Granted Jul 8, 2014

Semiconductor device, method for manufacturing the same, and electronic device

Inventors: Satoru Wakiyama (Kanagawa, JP); Hiroshi Ozaki (Kanagawa, JP)
Assignee: Sony Corporation
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Quick Facts
Patent No.
US 8,773,583
App. No.
13/086,830
Granted
Jul 8, 2014
Kind
B2
Abstract

Disclosed herein is a semiconductor device including: a first semiconductor chip having an electronic circuit section and a first connecting section formed on one surface thereof; a second semiconductor chip having a second connecting section formed on one surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the first and the second connecting sections connected to each other by a bump; a dam formed to fill a gap between the first and the second semiconductor chips on a part of an outer edge of the second semiconductor chip, the part of the outer edge being on a side of a region of formation of the electronic circuit section; and an underfill resin layer filled into the gap, protrusion of the resin layer from the outer edge of the second semiconductor chip to a side of the electronic circuit section being prevented by the dam.

Claims (37)

1. A semiconductor device comprising:

a first semiconductor chip having a solid-state imaging section formed at least on one surface of the first semiconductor chip, the first semiconductor chip having a first connecting section formed on a same surface as the surface of formation of said solid-state imaging section;

a second semiconductor chip having a second connecting section formed on one surface of the second semiconductor chip, the second semiconductor chip being mounted on said first semiconductor chip with said first connecting section and said second connecting section connected to each other by a bump;

a dam formed so as to fill a gap between said first semiconductor chip and said second semiconductor chip on at least a part of an outer edge of said second semiconductor chip, the part of the outer edge of said second semiconductor chip being on a side of a region of formation of said solid-state imaging section;

a bump section formed on the first semiconductor chip, wherein the bump section and the dam together form a ring shape; and

an underfill resin layer provided in the gap between said first semiconductor chip and said second semiconductor chip such that a protrusion of the underfill resin layer from the outer edge of said second semiconductor chip to a side of said solid-state imaging section is prevented by said dam, wherein the underfill resin layer includes a fillet located within an area formed by the ring shape.

2. The semiconductor device according to claim 1 , wherein said dam is formed by a same layer as a conductive layer forming said bump.

3. The semiconductor device according to claim 1 , wherein said dam is formed by a resin.

4. The semiconductor device according to claim 1 , wherein said solid-state imaging section and said second semiconductor chip are formed so as to be adjacent to each other.

5. The semiconductor device according to claim 1 , wherein said dam is formed in a shape along the outer edge of said second semiconductor chip.

6. A method for manufacturing a semiconductor device, said method comprising the steps of:

forming a solid-state imaging section at least on one surface of a first semiconductor chip;

forming a first connecting section on a same surface as the surface of formation of said solid-state imaging section;

forming a second connecting section on one surface of a second semiconductor chip;

mounting said second semiconductor chip on said first semiconductor chip with said first connecting section and said second connecting section connected to each other by a bump;

forming a dam for filling a gap between said first semiconductor chip and said second semiconductor chip on at least a part of an outer edge of said second semiconductor chip, the part of the outer edge of said second semiconductor chip being on a side of a region of formation of said solid-state imaging section;

forming a bump section on the first semiconductor chip, the bump section and the dam together forming a ring shape; and

forming an underfill resin layer so as to fill the underfill resin layer in the gap between said first semiconductor chip and said second semiconductor chip such that a protrusion of the underfill resin layer from the outer edge of said second semiconductor chip to a side of said solid-state imaging section is prevented by said dam, wherein forming the underfill resin layer includes forming a fillet located within an area formed by the ring shape.

7. The method for manufacturing the semiconductor device according to claim 6 , wherein in the step of forming said dam, said dam is formed by a same layer as a conductive layer forming said bump.

8. The method for manufacturing the semiconductor device according to claim 6 , wherein in the step of forming said dam, said dam is formed by a resin.

9. The method for manufacturing the semiconductor device according to claim 6 , wherein in the step of mounting said second semiconductor chip, said second semiconductor chip is mounted so as to be adjacent to said solid-state imaging section.

10. The method for manufacturing the semiconductor device according to claim 6 , wherein in the step of forming said dam, said dam is formed in a shape along the outer edge of said second semiconductor chip.

11. The method for manufacturing the semiconductor device according to claim 6 , wherein in the step of forming said underfill resin layer, said underfill resin layer is formed by laminating a resin film to a side of the surface of formation of the second connecting section of said second semiconductor chip and mounting said second semiconductor chip onto said first semiconductor chip.

12. An electronic device comprising:

a solid-state imaging device;

an optical system for guiding incident light to an imaging section of said solid-state imaging device; and

a signal processing circuit for processing an output signal of said solid-state imaging device;

wherein said solid-state imaging device includes:

a first semiconductor chip having a solid-state imaging section formed at least on one surface of the first semiconductor chip, the first semiconductor chip having a first connecting section formed on a same surface as the surface of formation of said solid-state imaging section;

a second semiconductor chip having a second connecting section formed on one surface of the second semiconductor chip, the second semiconductor chip being mounted on said first semiconductor chip with said first connecting section and said second connecting section connected to each other by a bump;

a dam formed so as to fill a gap between said first semiconductor chip and said second semiconductor chip on at least a part of an outer edge of said second semiconductor chip, the part of the outer edge of said second semiconductor chip being on a side of a region of formation of said solid-state imaging section;

a bump section formed on the first semiconductor chip, wherein the bump section and the dam together form a ring shape; and

an underfill resin layer provided in the gap between said first semiconductor chip and said second semiconductor chip such that a protrusion of the underfill resin layer from the outer edge of said second semiconductor chip to a side of said solid-state imaging section is prevented by said dam, wherein the underfill resin layer includes a fillet located within an area formed by the ring shape.

13. The electronic device according to claim 12 , wherein said dam is formed by a same layer as a conductive layer forming said bump.

14. The electronic device according to claim 12 , wherein said dam is formed by a resin.

15. The electronic device according to claim 12 , wherein said solid-state imaging section and said second semiconductor chip are formed so as to be adjacent to each other.

16. The electronic device according to claim 12 , wherein said dam is formed in a shape along the outer edge of said second semiconductor chip.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2011
From: WAKIYAMA, SATORU; OZAKI, HIROSHI
To: SONY CORPORATION
Reel/Frame 026127/0965 →
Priority Claims (1)
JP 2010-111910 · May 14, 2010 · national
Continuity (1)
Related Publication 20110279717A1 · Nov 17, 2011