Compression system and method for accelerating sparse matrix computations
View Patent ↗The present invention involves a sparse matrix processing system and method which uses sparse matrices that are compressed to reduce memory traffic and improve performance of computations using sparse matrices.
1. A method of improving the processing of sparse matrices by a computer system having a limited memory bandwidth, a processor capable of compressing and decompressing data, and a computer readable storage medium that can be used in connection with the processor, the method comprising:
applying, using the processor, a compression algorithm to compress row index data and column index data of a sparse matrix, the compression algorithm including
generating command codes and argument bytes for the matrix,
inserting a first command code between rows of the matrix,
for each low of the matrix, processing groups of up to four adjacent non-zero elements by encoding a position difference between adjacent groups as argument bytes, using a second command code for an argument greater than one byte corresponding to a size of the groups, and
packing the command codes and argument bytes into words including three command codes per word;
storing the compressed row and column index data of the sparse matrix; and
accessing, using the processor, the sparse matrix using a merged decompression/matrix-vector multiplication algorithm on the compressed index data and a vector.
2. The method of claim 1 , wherein processing involves document ranking.
3. The method of claim 2 , wherein document ranking uses a PageRank algorithm.
4. The method of claim 1 , wherein the matrix represents a graph.
5. The method of claim 1 , wherein processing involves solving a linear system of equations.
6. The method of claim 1 , wherein processing involves decomposition of the sparse matrix into pieces, assignment of processing of the pieces to separate processing elements, and concurrent overall computation by the processing elements to define a sequential portion of a parallel sparse matrix operation.
7. The method of claim 1 , wherein the sparse matrix represents a mesh representing the geometry of one or more objects.
8. The method of claim 1 , wherein the compression algorithm uses run-length encoding for the non-zero elements.
9. The method of claim 1 , wherein applying a compression algorithm includes generating indicator data having representations selected from the at least one of column index data and mw index data.
10. The method of claim 1 , further including producing a new vector from a product of the matrix and the vector.
11. A non-transitory computer-readable storage medium storing instructions that, when executed by one or more processors in a device for compressing and decompressing sparse matrices having matrix index data with rows and columns, cause the processor to:
apply a compression algorithm to compress both the mw and column matrix index data of a sparse matrix, the compression algorithm including
generating command codes and argument bytes for the matrix,
inserting a first command code between rows of the matrix,
for each mw of the matrix, processing groups of up to four adjacent non-zero elements by encoding a position difference between adjacent groups as argument bytes, using a second command code for an argument greater than one byte and a third command code corresponding to a size of the groups, and
packing the command codes and argument bytes into words including three command codes per word;
store the matrix index data in the compressed format; and
use a merged decompression/matrix-vector multiplication algorithm on the compressed matrix index data and a vector to access the sparse matrix.
12. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions further cause the processor to process the sparse matrix using document ranking.
13. The non-transitory computer-readable storage medium of claim 12 , wherein the ranking is uses a PageRank algorithm.
14. The non-transitory computer-readable storage medium of claim 11 , wherein the sparse matrix represents a graph.
15. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions further cause the processor to process the sparse matrix by solving a linear system of equations.
16. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions further cause the processor to process the sparse matrix by decomposing the sparse matrix into pieces, assigning processing of the pieces to separate processing elements, and concurrently performing an overall computation by the processing elements to define a sequential portion of a parallel sparse matrix operation.
17. The non-transitory computer-readable storage medium of claim 11 , wherein the sparse matrix represents a mesh representing the geometry of one or more objects.
18. The non-transitory computer-readable storage medium of claim 11 , wherein each index data value is represented in the compressed matrix index data using one of a set of two or more encoding algorithms.
19. The non-transitory computer-readable storage medium of claim 11 , wherein the compression algorithm uses run-length encoding for the non-zero elements.
20. The non-transitory computer-readable storage medium of claim 11 , wherein applying a compression algorithm includes causing the processor to store indicator data for multiple row and/or column index data elements together within a single unit of storage, and wherein using a merged decompression/matrix-vector multiplication algorithm includes the processor using the indicator data for multiple row and/or column index data elements to choose a location to which to change a flow of instruction execution of the processor.
21. The method of claim 9 , wherein applying a compression algorithm includes storing the indicator data for multiple row and/or column index data elements together within a single unit of storage, and wherein using a merged decompression/matrix-vector multiplication algorithm includes using the indicator data for multiple row and/or column index data elements to choose a location to which to change a flow of instruction execution of the processor.
22. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions further cause the processor to produce a new vector from a product of the matrix and the vector.