Transistors and electronic devices including the same
A transistor includes a first active layer having a first channel region and a second active layer having a second channel region. A first gate of the transistor is configured to control electrical characteristics of at least the first active layer and a second gate is configured to control electrical characteristics of at least the second active layer. A source electrode contacts the first and second active layers. A drain electrode also contacts the first and second active layers.
1. A transistor comprising:
a first active layer including a first channel region;
a second active layer including a second channel region;
a first gate to control electrical characteristics of at least the first active layer;
a second gate to control electrical characteristics of at least the second active layer;
a source electrode contacting the first and second active layers; and
a drain electrode contacting the first and second active layers; wherein at least a portion of the source electrode and at least a portion of the drain electrode is disposed between the first active layer and the second active layer.
2. The transistor of claim 1 , wherein an end portion of the source electrode is disposed between the first and second active layers, and an end portion of the drain electrode is disposed between the first and second active layers.
3. The transistor of claim 1 , wherein portions of the first and second active layers between the source electrode and the drain electrode contact each other.
4. The transistor of claim 1 , wherein at least one of the first and second active layers includes an oxide semiconductor.
5. The transistor of claim 1 , wherein at least one of the first and second active layers includes a non-oxide semiconductor.
6. The transistor of claim 1 , wherein one of the first and second active layers includes an oxide semiconductor, whereas an other of the first and second active layers includes a non-oxide semiconductor.
7. The transistor of claim 1 , wherein the first and second active layers are disposed between the first and second gates.
8. The transistor of claim 1 , wherein at least one of the first and second active layers covers an entire surface of at least one of the source electrode and the drain electrode.
9. The transistor of claim 1 , wherein the first and second gates are electrically connected to each other.
10. The transistor of claim 1 , wherein the first and second gates are electrically insulated from each other.
11. The transistor of claim 1 , wherein a middle portion of the first and second active layers contact one another.
12. The transistor of claim 1 , further comprising:
a first gate insulating layer formed on an upper surface of the first gate; wherein
the first active layer is formed on an upper surface of the first gate insulating layer,
the source electrode is formed on the first gate insulating layer and an upper surface of a first end portion of the first active layer,
the drain electrode is formed on the first gate insulating layer and an upper surface of a second end portion of the first active layer, and
the second active layer is formed on an upper surface of a middle portion of the first active layer, an upper surface of a portion of the source electrode corresponding to the first end portion of the first active layer, and an upper surface of a portion of the drain electrode corresponding to the second end portion of the first active layer.
13. The transistor of claim 1 , further comprising:
a first gate insulating layer formed on an upper surface of the first gate; wherein
the first active layer is formed on an upper surface of the first gate insulating layer, and
the source electrode, the drain electrode and a portion of the second active layer are formed on an upper surface of the first active layer.
14. A method of operating the transistor of claim 1 , the method comprising:
applying a voltage to at least one of the first and second gates.
15. A method of operating the transistor of claim 1 , the method comprising:
selectively activating and deactivating the transistor by independently controlling electrical characteristics of the first and second active layers.
16. An electronic device comprising the transistor of claim 1 .
17. The transistor of claim 7 , wherein the first active layer is disposed closer to the first gate than the second active layer.
18. The transistor of claim 11 , wherein a first end portion of the second active layer is formed on an upper surface of the source electrode, and a second end portion of the second active layer is formed on an upper surface of the drain electrode.
19. The transistor of claim 11 , wherein an end portion of the source electrode is formed between the first and second active layers, and an end portion of the drain electrode is formed between the first and second active layers.
20. The transistor of claim 12 , further comprising:
a second gate insulating layer formed on an upper surface of the source electrode, the drain electrode and the second active layer; wherein
the second gate is formed on an upper surface of the second gate insulating layer.
21. The method of claim 14 , wherein a same voltage is applied to each of the first and second gates.
22. The method of claim 14 , wherein a different voltage is applied to each of the first and second gates.
23. The method of claim 14 , wherein one of a turn-on voltage and a turn-off voltage is applied to each of the first and second gates.
24. The method of claim 14 , wherein a turn-on voltage is applied to one of the first and second gates, and a turn-off voltage is applied to an other one of the first and second gates.
25. The method of claim 15 , wherein the electrical characteristics are independently controlled by selectively applying voltages to the first and second gates.
26. The electronic device of claim 16 , wherein the electronic device is a flat panel display device.
27. The transistor of claim 17 , wherein the second active layer is disposed closer to the second gate than the first active layer.
28. A method of manufacturing a transistor, the method comprising:
forming a first gate;
forming a first gate insulating layer covering the first gate;
forming a first active layer on the first gate insulating layer;
forming a source electrode to contact a first region of the first active layer, and a drain electrode to contact a second region of the first active layer;
forming a second active layer on the first active layer to cover at least a portion of the source electrode and the drain electrode;
forming a second gate insulating layer to cover the second active layer; and
forming a second gate on the second gate insulating layer.
29. The method of claim 28 , further comprising:
forming a first semiconductor layer on the first gate insulating layer;
patterning the first semiconductor layer to form the first active layer;
forming the source electrode and the drain electrode that contact the first active layer;
forming a second semiconductor layer to cover the first active layer, the source electrode, and the drain electrode; and
patterning the second semiconductor layer to form the second active layer.
30. The method of claim 28 , further comprising:
forming a first semiconductor layer on the first gate insulating layer;
forming the source electrode and the drain electrode on the first semiconductor layer;
forming a second semiconductor layer to cover the first semiconductor layer, the source electrode, and the drain electrode; and
patterning the second semiconductor layer and the first semiconductor layer to form the first and second active layers.
31. The method of claim 28 , wherein at least one of the first and second active layers includes an oxide semiconductor.
32. The method of claim 28 , wherein at least one of the first and second active layers includes a non-oxide semiconductor.
33. The method of claim 28 , wherein one of the first and second active layers includes an oxide semiconductor, and an other one of the first and second active layers includes a non-oxide semiconductor.