IP Library › Granted Patent US 8,779,518
Granted Patent B2
US 8,779,518 · App. 13/693,294 · Granted Jul 15, 2014

Apparatus for ESD protection

Inventors: Wun-Jie Lin (Hsin-Chu, TW); Bo-Ting Chen (Fengyuan, TW); Jen-Chou Tseng (Jhudong Township, TW); Ming-Hsiang Song (Shin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 8,779,518
App. No.
13/693,294
Granted
Jul 15, 2014
Kind
B2
Abstract

A structure comprises an N+ region formed over a substrate, a P+ region formed over the substrate, wherein the P+ region and the N+ region form a diode and a first epitaxial growth block region formed between the N+ region and the P+ region.

Claims (69)

1. A structure comprising:

an N+ region formed over a substrate;

a P+ region formed over the substrate, wherein the P+ region and the N+ region form a diode; and

a first epitaxial growth block region formed between the N+ region and the P+ region, wherein the first epitaxial growth block region comprises silicon nitride.

2. The structure of claim 1 , wherein:

the N+ region is formed in an n-well of the substrate; and

the P+ region is formed in the n-well of the substrate, and wherein the N+ region and the P+ region form a p-type electrostatic discharge (ESD) protection diode.

3. The structure of claim 1 , wherein:

the N+ region is formed in a p-well of the substrate; and

the P+ region is formed in the p-well of the substrate, and wherein the N+ region and the P+ region form an n-type ESD protection diode.

4. The structure of claim 1 , further comprising:

a second epitaxial growth block region formed on an opposite side of the N+ region with respect to the first epitaxial growth block region; and

a third epitaxial growth block region formed on an opposite side of the P+ region with respect to the first epitaxial growth block region.

5. The structure of claim 4 , wherein:

the second epitaxial growth block region comprises silicon nitride; and

the third epitaxial growth block region comprises silicon nitride.

6. The structure of claim 1 , wherein:

the first epitaxial growth block region is of a width approximately equal to 144 nm.

7. A system comprising:

an integrated circuit comprising:

a first terminal coupled to a first voltage rail;

a second terminal coupled to an input/output pad; and

a third terminal coupled to a second voltage rail;

a first electrostatic discharge (ESD) protection diode coupled between the first voltage rail and the input/output pad, wherein the first ESD protection diode comprises:

a first N+ region formed in an n-well of a substrate;

a first P+ region formed in the n-well of the substrate; and

a first epitaxial growth block region formed between the first N+ region and the first P+ region; and

a second ESD protection diode coupled between the second voltage rail and the input/output pad, wherein the second ESD protection diode comprises:

a second N+ region formed in a p-well of the substrate;

a second P+ region formed in the p-well of the substrate; and

a second epitaxial growth block region formed between the second N+ region and the second P+ region.

8. The system of claim 7 , wherein:

the first epitaxial growth block region comprises silicon nitride; and

the second epitaxial growth block region comprises silicon nitride.

9. The system of claim 7 , wherein:

the first voltage rail is connected to a power source; and

the second voltage rail is connected to ground.

10. The system of claim 7 , wherein:

the first N+ region is coupled to the first voltage rail;

the first P+ region is coupled to the input/output pad;

the second N+ region is coupled to the input/output pad; and

the second P+ region is coupled to the second voltage rail.

11. The system of claim 7 , further comprising:

a plurality of p-type ESD protection diodes connected in parallel with the first ESD protection diode; and

a plurality of n-type ESD protection diodes connected in parallel with the second ESD protection diode.

12. The system of claim 11 , wherein:

each active region of the plurality of p-type ESD protection diodes is separated from an adjacent active region by an epitaxial growth block region; and

each active region of the plurality of n-type ESD protection diodes is separated from an adjacent active region by the epitaxial growth block region.

13. The system of claim 7 , wherein:

the first ESD protection diode is a p-type ESD protection diode having an anode coupled to the input/output pad and a cathode coupled to the first voltage rail.

14. The system of claim 7 , wherein:

the second ESD protection diode is an n-type ESD protection diode having an anode coupled to the second voltage rail and a cathode coupled to the input/output pad.

15. A method comprising:

forming an active region including a plurality of fins;

depositing an epitaxial growth block layer over the active region;

patterning the epitaxial growth block layer to define a first growth area for an N+ region and a second growth area for a P+ region;

removing portions of the active region in the first growth area and the second growth area; and

growing the N+ region and the P+ region through an epitaxial growth process, wherein the N+ region and the P+ region form an electrostatic discharge (ESD) protection diode.

16. The method of claim 15 , wherein:

the N+ region is formed in a p-well of a substrate; and

the P+ region is formed in the p-well of the substrate, and wherein the N+ region and the P+ region form an n-type ESD protection diode.

17. The method of claim 15 , wherein:

the N+ region is formed in an n-well of a substrate; and

the P+ region is formed in the n-well of the substrate, and wherein the N+ region and the P+ region form a p-type ESD protection diode.

18. The method of claim 15 , further comprising:

forming a first contact on the N+ region, wherein the first contact is a cathode of the ESD protection diode; and

forming a second contact on the P+ region, wherein the second contact is an anode of the ESD protection diode.

19. The method of claim 15 , wherein:

the epitaxial growth block layer comprises silicon nitride.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2012
From: LIN, WUN-JIE; CHEN, BO-TING; TSENG, JEN-CHOU; SONG, MING-HSIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 029400/0260 →
Continuity (1)
Related Publication 20140151809A1 · Jun 5, 2014