IP Library Granted Patent US 8,781,033
Granted Patent B2
US 8,781,033 · App. 13/533,207 · Granted Jul 15, 2014

Apparatus and method for breaking trapping sets

Inventors: Yang Han (Sunnyvale, CA); Shaohua Yang (San Jose, CA); Fan Zhang (Milpitas, CA); Zongwang Li (Dublin, CA)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,781,033
App. No.
13/533,207
Granted
Jul 15, 2014
Kind
B2
Abstract

An error correction data processing apparatus includes a noise predictive calibration circuit operable to calibrate a first set of filter coefficients based on a first data set and a second set of filter coefficients based on a second data set, and includes a first noise predictive detector operable to receive the first set of filter coefficients. The apparatus further includes a decoder operable to perform a first global iteration with the first noise predictive detector and determine a violation check count value, and a second noise predictive detector operable to receive the second set of filter coefficients if the violation check count value is less than a predetermined value or receive the first set of filter coefficients if the violation check count value is greater than the predetermined value.

Claims (40)

1. An error correction data processing apparatus comprising:

a noise predictive calibration circuit configured to calibrate a first set of filter coefficients based on a first data set and a second set of filter coefficients based on a second data set;

a first noise predictive detector configured to receive the first set of filter coefficients;

a decoder configured to perform a first global iteration with the first noise predictive detector and determine a violation check count value; and

a second noise predictive detector configured to receive the second set of filter coefficients if the violation check count value is less than a predetermined value or receive the first set of filter coefficients if the violation check count value is greater than the predetermined value.

2. The apparatus of claim 1 , wherein the decoder and the second noise predictive detector are configured to perform a second and above global iterations based on the second set of filter coefficients.

3. The apparatus of claim 1 , wherein the second detector is modified by the second set of filter coefficients during detection in the second and above global iterations between the second noise predictive detector and the decoder if the violation check count value is less than the predetermined value.

4. The apparatus of claim 1 further comprising:

a first buffer configured to store the first set of filter coefficients;

a second buffer configured to store the second set of coefficients; and

a multiplexer configured to switch between loading the first set of filter coefficients or the second set of filter coefficients to the second noise predictive detector.

5. The apparatus of claim 4 further comprising a comparator configured to trigger the multiplexer to switch between loading either the first set of filter coefficients or the second set of filter coefficients based on the violation check count value and the predetermined value.

6. The apparatus of claim 1 further comprising a loading circuit configured to load filter coefficients into the first noise predictive detector and into the second noise predictive detector.

7. The apparatus of claim 1 , wherein the first noise predictive detector and the second noise predictive detector each comprise a soft output Viterbi algorithm detector (SOVA), or each comprise a maximum a posteriori (MAP) algorithm detector.

8. The apparatus of claim 1 , wherein the decoder comprises a Low Density Parity Check (LDPC) algorithm.

9. The apparatus of claim 1 , wherein the noise predictive calibration circuit applies a Least Mean Squares (LMS) algorithm to calibrate the first set of filter coefficients and the second set of filter coefficients.

10. The apparatus of claim 1 wherein the violation check count value represents a trapping set.

11. The apparatus of claim 1 wherein the predetermined value represents a type of error event.

12. The apparatus of claim 1 , wherein at least a portion of the data processing apparatus is fabricated in at least one integrated circuit.

13. A method for improving error correction in a data processing system, the method comprising steps of:

calibrating a first set of filter coefficients based on a first data set and calibrating a second set of filter coefficients based on a second data set;

receiving, by a first noise predictive detector, the first set of filter coefficients;

performing a first global iteration with the first noise predictive detector and a decoder and determining a violation check count value; and

receiving, by a second noise predictive detector, the second set of filter coefficients if the violation check count value is less than a prescribed value or the first set of filter coefficients if the violation check count value is greater than the prescribed value.

14. The method of claim 13 , further comprising performing a second and above global iterations based on the second set of filter coefficients between the decoder and the second noise predictive detector.

15. The method of claim 13 , further comprising modifying the second noise predictive detector with the second set of filter coefficients during detection in the second and above global iterations between the second noise predictive detector and the decoder if the violation check count value is less than the prescribed value.

16. The method of claim 13 , further comprising:

storing in a first buffer the first set of filter coefficients;

storing in a second buffer the second set of coefficients; and

switching between loading the first set of filter coefficients or the second set of filter coefficients to the second noise predictive detector.

17. The method of claim 16 , further comprising loading one of the first set of filter coefficients and the second set of filter coefficients as a function of the violation check count value and the prescribed value.

18. The method of claim 13 , further comprising applying, by both the first noise predictive detector and the second predictive detector, a soft output Viterbi algorithm (SOVA) or applying a maximum a posteriori (MAP) algorithm.

19. The method of claim 13 , further comprising applying a Low Density Parity Check (LDPC) by the decoder.

20. The method of claim 13 , wherein the calibrating step further comprises applying a Least Mean Squares (LMS) algorithm.

21. The method of claim 13 , wherein the violation check count value represents a trapping set.

22. The method of claim 13 , wherein the prescribed value represents a type of error event.

23. A data processing system including first and second noise predictive detectors, the data processing system comprising:

memory; and

at least one processor coupled with the memory and operative: to obtain at least first and second data sets; to calibrate a first set of filter coefficients based on the first data set and to calibrate a second set of filter coefficients based on the second data set; to receive, by the first noise predictive detector, the first set of filter coefficients; to perform a first global iteration with the first noise predictive detector and a decoder and determining a violation check count value; and to receive, by the second noise predictive detector, the second set of filter coefficients if the violation check count value is less than a prescribed value or the first set of filter coefficients if the violation check count value is greater than the prescribed value.

24. An article of manufacture comprising a computer program product, said computer program product in turn comprising a non-transitory computer readable storage medium storing in a non-transitory manner executable program instructions which, when executed, implement the steps of a method according to claim 13 .

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2012
From: HAN, YANG; YANG, SHAOHUA; ZHANG, FAN; LI, ZONGWANG
To: LSI CORPORATION
Reel/Frame 028444/0389 →
Continuity (1)
Related Publication 20130343495A1 · Dec 26, 2013