Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a channel region in a workpiece; and
forming a source or drain region proximate the channel region comprising:
recessing the workpiece proximate the channel region using an etch process;
forming a first conformal liner having a first material composition on a bottom surface of the recess;
forming a second conformal liner having a second material composition on sidewalls of the recess, the second material composition being different than the first material composition; and
forming a contact resistance-lowering material layer and a channel-stressing material layer in the recess, wherein the contact resistance-lowering material layer comprises SiP, SiAs, or a silicide, and wherein the channel-stressing material layer comprises SiCP or SiCAs.
2. The method according to claim 1 , wherein forming the source or drain region comprises forming the contact resistance-lowering material layer over the channel-stressing material layer.
3. The method according to claim 1 , wherein forming the source or drain region comprises forming the channel-stressing material layer over the contact resistance-lowering material layer.
4. The method according to claim 3 , wherein forming the contact resistance-lowering material layer comprises forming a first contact resistance-lowering material layer, further comprising forming a second contact resistance-lowering material layer over the channel-stressing material layer.
5. The method according to claim 1 , wherein forming the channel region comprises forming SiGe or a III-V material.
6. The method according to claim 1 , wherein forming the contact resistance-lowering material layer or the channel-stressing material layer does not include an implantation process or an anneal process.
7. The method according to claim 1 , wherein the etch process comprises an anisotropic component.
8. The method according to claim 1 , wherein forming the source or drain region comprises forming a source or drain region that is spaced apart from the channel region by about 20 nm or less at a widest point of the source or drain region.
9. A method of manufacturing a semiconductor device, the method comprising:
providing a workpiece;
forming a channel region in the workpiece;
forming a gate dielectric over the channel region;
forming a gate over the gate dielectric; and
forming a source region and a drain region proximate the channel region comprises:
epitaxially growing a contact resistance-lowering material layer comprising SiP or SiAs, the contact resistance-lowering material layer having a substantially uniform thickness; and
epitaxially growing a channel-stressing material layer comprising SiCP or SiCAs on the contact resistance-lowering material layer.
10. The method according to claim 9 , wherein forming the semiconductor device comprises forming a fin field effect transistor (FinFET) or a planar transistor.
11. The method according to claim 9 , wherein forming the source region and the drain region comprise forming recesses in the workpiece, further comprising:
forming a first liner on bottom surfaces of the recesses; and
forming a second liner on sidewalls of the recesses.
12. The method according to claim 11 , wherein forming the first liner comprises forming SiP, and wherein forming the second liner comprises forming SiAs.
13. The method according to claim 9 , wherein forming the source region and the drain region comprises using AsH 3 as a dopant gas.
14. A semiconductor device, comprising:
a transistor including:
a channel region disposed in a workpiece;
a gate dielectric disposed over the channel region;
a gate disposed over the gate dielectric; and
a source region and a drain region proximate the channel region, the source region and the drain region being disposed in recesses, the source region and the drain region including:
a first conformal liner having a first material composition on bottom surfaces of the recesses;
a second conformal liner having a second material composition on sidewalls of the recesses, the second material composition being different than the first material composition;
a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide; and
a channel-stressing material layer comprising SiCP or SiCAs.
15. The semiconductor device according to claim 14 , wherein the channel region comprises a fin of semiconductive material.
16. The semiconductor device according to claim 15 , wherein the recesses in the workpiece are proximate the fin of semiconductive material.
17. The semiconductor device according to claim 16 , wherein the fin comprises a height comprising a first dimension within the workpiece, wherein the recess comprises a depth comprising a second dimension, and wherein the second dimension comprises about twice the first dimension or greater.
18. The semiconductor device according to claim 17 , wherein the contact resistance-lowering material layer is disposed over the channel-stressing material layer, and wherein the second dimension comprises about thrice the first dimension or greater.
19. The semiconductor device according to claim 18 , wherein a boundary between the contact resistance-lowering material layer and the channel-stressing material layer is disposed proximate a bottom of the channel region.
20. The method of claim 1 , wherein forming the first conformal liner comprises forming SiP, and wherein forming the second conformal liner comprises forming SiAs.