IP Library › Granted Patent US 8,786,039
Granted Patent B2
US 8,786,039 · App. 13/723,172 · Granted Jul 22, 2014

Method and system for providing magnetic junctions having engineered perpendicular magnetic anisotropy

Inventors: Dmytro Apalkov (San Jose, CA); Chang-Man Park (Los Altos, CA); Roman Chepulskyy (Milpitas, CA); Alexey Vasilyevitch Khvalkovskiy (Milpitas, CA); Xueti Tang (San Jose, CA)
Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 8,786,039
App. No.
13/723,172
Granted
Jul 22, 2014
Kind
B2
Abstract

A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a reference layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The free layer has an engineered perpendicular magnetic anisotropy. The engineered PMA includes at least one of an insulating insertion layer induced PMA, a stress induced PMA, PMA due to interface symmetry breaking, and a lattice mismatch induced PMA. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Claims (65)

1. A magnetic junction for use in a magnetic device comprising:

a reference layer;

a nonmagnetic spacer layer; and

a free layer having an engineered perpendicular magnetic anisotropy (PMA), the free layer including a plurality of magnetic layers, the plurality of magnetic layers including at least one oxide layer and a plurality of conductive layers, the at least one oxide layer being ferromagnetic, interleaved with the plurality of conductive layers and sandwiched between the plurality of conductive layers, the nonmagnetic spacer layer being between the reference layer and the free layer, the engineered PMA including at least one of an insulating insertion layer induced PMA, a stress induced PMA, PMA due to interface symmetry breaking, and a lattice mismatch induced PMA;

wherein the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

2. The magnetic junction of claim 1 wherein the engineered PMA includes the insulating insertion layer PMA.

3. The magnetic junction of claim 2 wherein the at least one oxide layer includes at least one nickel oxide layer.

4. The magnetic junction of claim 3 wherein the free layer further includes at least one Ni layer adjoining the nickel oxide layer.

5. The magnetic junction of claim 1 wherein the engineered PMA includes the stress induced PMA and wherein the magnetic junction further includes:

a stress inducing layer, and

a capping layer adjoining the free layer and residing between the free layer and the at least one stress inducing layer.

6. The magnetic junction of claim 5 wherein the capping layer includes MgO and the stress inducing layer includes Ru.

7. The magnetic junction of claim 5 wherein the free layer further includes:

a plurality of magnetic layers, the plurality of magnetic layers including at least one oxide layer and a plurality of conductive layers, the at least one oxide layer sandwiched between the plurality of conductive layers.

8. The magnetic junction of claim 5 further comprising:

an additional stress inducing layer, the reference layer, the free layer and the nonmagnetic spacer layer being between the additional stress inducing layer and the stress inducing layer.

9. The magnetic junction of claim 8 wherein the stress inducing layer has a first coefficient of thermal expansion and the additional stress inducing layer has a second coefficient of thermal expansion different from the first coefficient of thermal expansion.

10. The magnetic junction of claim 8 wherein the stress inducing layer and the additional stress inducing layer provide a gradient in a stress of the free layer.

11. The magnetic junction of claim 5 wherein the stress inducing layer provides a compressive stress on the free layer.

12. The magnetic junction of claim 5 wherein the stress inducing layer provides a tensile stress on the free layer.

13. The magnetic junction of claim 1 wherein the engineered PMA includes the lattice mismatch induced PMA, the free layer and the nonmagnetic spacer layer having a lattice mismatch of greater than 5.3%.

14. The magnetic junction of claim 13 wherein the free layer further includes at least one of Fe 1-s R s , Co t Fe 1-t-u M u , Co y Fe 1-x-y-z B z M x and a modified Heusler alloy, where R is at least one of Al, Ti, Zr, Hf, and Zn and where M is at least one of Al, Bi, Ta, Ti, Zr, Hf, Mo, W, Si, Ge, Sn and Zn.

15. The magnetic junction of claim 13 wherein the nonmagnetic spacer layer further includes at least one of WO, MgO, TiO, VO, and MgO.

16. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including at least one magnetic junction, the at least one magnetic junction including a pinned layer, a nonmagnetic spacer layer, and a free layer, the free layer having an engineered perpendicular magnetic anisotropy (PMA), the nonmagnetic spacer layer being between the pinned layer and the free layer, the engineered PMA including at least one of an insulating insertion layer induced PMA, a stress induced PMA, PMA due to interface symmetry breaking, and a lattice mismatch induced PMA, the free layer including a plurality of magnetic layers, the plurality of magnetic layers including at least one oxide layer and a plurality of conductive layers, the at least one oxide layer being ferromagnetic, interleaved with the plurality of conductive layers and sandwiched between the plurality of conductive layers, the magnetic junction being configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction; and

a plurality of bit lines.

17. The magnetic memory of claim 16 wherein the engineered PMA includes the insulating insertion layer PMA.

18. The magnetic memory of claim 17 wherein the at least one oxide layer includes at least one nickel oxide layer.

19. The magnetic memory of claim 18 wherein the free layer further includes at least one Ni layer adjoining the nickel oxide layer.

20. The magnetic memory of claim 16 wherein the engineered PMA includes the stress induced PMA and wherein the magnetic junction further includes:

a stress inducing layer, and

a capping layer adjoining the free layer and residing between the free layer and the at least one stress inducing layer.

21. The magnetic memory of claim 20 wherein the capping layer includes MgO and the stress inducing layer includes Ru.

22. The magnetic memory of claim 20 wherein the free layer further includes:

a plurality of magnetic layers, the plurality of magnetic layers including at least one oxide layer and a plurality of conductive layers, the at least one oxide layer sandwiched between the plurality of conductive layers.

23. The magnetic memory of claim 20 further comprising:

an additional stress inducing layer, the reference layer, the free layer and the nonmagnetic spacer layer being between the additional stress inducing layer and the stress inducing layer.

24. The magnetic memory of claim 23 wherein the stress inducing layer has a first coefficient of thermal expansion and the additional stress inducing layer has a second coefficient of thermal expansion different from the first coefficient of thermal expansion.

25. The magnetic memory of claim 23 wherein the stress inducing layer and the additional stress inducing layer provide a gradient in a stress the free layer.

26. The magnetic memory of claim 20 wherein the stress inducing layer provides a compressive stress on the free layer.

27. The magnetic memory of claim 20 wherein the stress inducing layer provides a tensile stress on the free layer.

28. The magnetic memory of claim 16 wherein the engineered PMA includes the lattice mismatch induced PMA, the free layer and the nonmagnetic spacer layer having a lattice mismatch of greater than 5.3%.

29. The magnetic memory of claim 28 wherein the free layer further includes at least one of Fe 1-s R s , Co t Fe 1-t-u M u , Co y Fe 1-x-y-z B z M x and a modified Heusler alloy, where R is at least one of Al, Ti, Zr, Hf, and Zn and where M is at least one of Al, Bi, Ta, Ti, Zr, Hf, Mo, W, Si, Ge, Sn and Zn.

30. The magnetic memory of claim 28 wherein the nonmagnetic spacer layer further includes at least one of WO, MgO, TiO, VO, and MgO.

31. A method for providing a magnetic junction for use in a magnetic device comprising:

providing a pinned layer;

providing a nonmagnetic spacer layer; and

providing a free layer having an engineered perpendicular magnetic anisotropy (PMA), the nonmagnetic spacer layer being between the pinned layer and the free layer, the engineered PMA including at least one of an insulating insertion layer induced PMA, a stress induced PMA, PMA due to interface symmetry breaking, and a lattice mismatch induced PMA, the step or providing the free layer including providing a plurality of magnetic layers, the plurality of magnetic layers including at least one oxide layer and a plurality of conductive layers, the at least one oxide layer being ferromagnetic, interleaved with the plurality of conductive layers and sandwiched between the plurality of conductive layers;

wherein the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

32. The method of claim 31 wherein the engineered PMA includes the insulating insertion layer PMA.

33. The method of claim 32 wherein the at least one oxide layer includes at least one nickel oxide layer.

34. The method of claim 33 wherein the step of providing the plurality of magnetic layers further includes:

depositing a nickel layer;

oxidizing the nickel layer.

35. The method of claim 31 wherein the engineered PMA includes the stress induced PMA and wherein the method further includes:

providing a stress inducing layer, and

providing a capping layer adjoining the free layer and residing between the free layer and the at least one stress inducing layer.

36. The method of claim 35 wherein the capping layer includes MgO and the stress inducing layer includes Ru.

37. The method of claim 35 wherein the magnetic junction is fabricated on a substrate and wherein the step of providing the free layer further includes:

heating the substrate to a temperature above room temperature; and

depositing the free layer on the substrate while the substrate is at the temperature.

38. The method of claim 35 further comprising:

an additional stress inducing layer, the reference layer, the free layer and the nonmagnetic spacer layer being between the additional stress inducing layer and the stress inducing layer.

39. The method of claim 31 wherein the engineered PMA includes the lattice mismatch induced PMA, the free layer and the nonmagnetic spacer layer having a lattice mismatch of greater than 5.3%.

40. The method of claim 39 wherein the free layer further includes at least one of Fe 1-s R s , Co t Fe 1-t-u M u , Co y Fe 1-x-y-z B z M x and a modified Heusler alloy, where R is at least one of Al, Ti, Zr, Hf, and Zn and where M is at least one of Al, Bi, Ta, Ti, Zr, Hf, Mo, W, Si, Ge, Sn and Zn.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2012
From: APALKOV, DMYTRO; PARK, CHANG-MAN; CHEPULSKYY, ROMAN; KHVALKOVSKIY, ALEXEY VASILYEVITCH; TANG, XUETI
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 029514/0595 →
Continuity (1)
Related Publication 20140175582A1 · Jun 26, 2014