Layer formation with reduced channel loss
Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.
1. A method, comprising:
forming a first insulating layer over a gate region and a semiconductor device region;
forming a second insulating layer over the first insulating layer;
forming a third insulating layer over the second insulating layer;
etching a portion of the third insulating layer using a first etching process, wherein the second insulating layer protects the semiconductor device region during the first etching process;
etching a portion of the first insulating layer beneath the etched portion of the third insulating layer using at least a second etching process, wherein the second etching process comprises a wet etching process; and
after etching the portion of the first insulating layer, removing a remaining portion of the second insulating layer and a remaining portion of the third insulating layer such that one or more portions of the first insulating layer remains.
2. The method of claim 1 , wherein the second insulating layer comprises a different insulating material than the first and third insulating layers.
3. The method of claim 2 , wherein forming the first layer comprises forming a first layer comprising silicon nitride.
4. The method of claim 2 , wherein forming the second layer comprises forming a second layer comprising silicon oxide.
5. The method of claim 2 , wherein forming the third layer comprises forming a third layer comprising silicon nitride.
6. The method of claim 1 , wherein the etching of the portion of the first insulating layer substantially does not etch the semiconductor device region.
7. The method of claim 1 , further comprising doping the semiconductor device region through at least a portion of the first insulating layer.
8. The method of claim 1 , wherein,
forming the first layer comprises forming a first layer comprising silicon nitride,
forming the second layer comprises forming a second layer comprising silicon oxide, and
forming the third layer comprises forming a third layer comprising silicon nitride.
9. The method of claim 8 , wherein the etching of the portion of the third insulating layer comprises using a dry etching process.
10. The method of claim 9 , wherein the dry etching process comprises reactive ion etching.
11. The method of claim 1 , further comprising:
etching a portion of the second insulating layer beneath the etched portion of the third insulating layer using at least the second etching process.
12. The method of claim 1 , wherein the second etching process is different from the first etching process.
13. The method of claim 12 , wherein the etching of the portion of the third insulating layer comprises using a dry etching process.