IP Library Granted Patent US 8,796,698
Granted Patent B2
US 8,796,698 · App. 11/638,406 · Granted Aug 5, 2014

Method for fabricating substrate with nano structures, light emitting device and manufacturing method thereof

Inventors: Jong Wook Kim (Seongnam-si, KR); Hyun Kyong Cho (Seoul, KR)
Assignees: LG Electronics Inc.; LG Innotek Co., Ltd.
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Quick Facts
Patent No.
US 8,796,698
App. No.
11/638,406
Granted
Aug 5, 2014
Kind
B2
Abstract

A method of fabricating a substrate with nano structures, light emitting device using the substrate and a manufacturing method thereof, wherein a substrate for growing a light emitting device is formed with nano agglomerations, and the substrate is etched by using the agglomerations as a mask to allow nano structures to be formed on the substrate, thereby enabling to grow a crystal defect-reduced, reliability-improved, good quality light emitting structure, and wherein the light emitting structure is formed with nano structures to enhance the light extraction efficiency.

Claims (25)

1. A vertical semiconductor light emitting element comprising:

a first semiconductor layer with a plurality of nano structures thereunder having a first polarity;

an active layer on the first semiconductor layer;

a second semiconductor layer on the active layer having a second polarity opposite the first polarity;

a first electrode on some of the nano structures of the first semiconductor layer;

a second electrode on the second semiconductor layer, the second electrode including a reflective ohmic electrode on an entire area of the second semiconductor layer, and a metal layer on a portion of the reflective ohmic electrode; and

a support directly contacting the metal layer configured to support the metal layer, wherein a center portion of the second electrode is vertically aligned with a center portion of the first electrode.

2. The element of claim 1 , wherein the first semiconductor layer includes a GaN semiconductor.

3. The element of claim 1 , wherein the second semiconductor layer includes a GaN semiconductor.

4. The element of claim 1 , wherein the metal layer of the second electrode is formed at a same area corresponding to that of the first electrode.

5. The element of claim 1 , wherein a size of the metal layer of the second electrode corresponds to that of the first electrode.

6. The element of claim 1 , wherein the nano structure includes a nano rod.

7. The element of claim 6 , wherein a width of the nano rod is in the range of about 10 nm to 2,000 nm.

8. The element of claim 1 , wherein the nano structure includes a nano groove.

9. The element of claim 1 , wherein the nano structure includes a mixture of a nano rod and a nano groove.

10. The element of claim 1 , wherein the first polarity includes an n-type.

11. The element of claim 10 , wherein the second polarity includes a p-type.

12. The element of claim 1 , wherein the first electrode is positioned both on some of the nano structures and a portion of the first semiconductor layer where the nano structures are not formed.

13. The element of claim 1 , wherein the first electrode is positioned on the nano structures.

14. The element of claim 1 , wherein the first electrode is positioned on an entire area of the first semiconductor layer.

15. The element of claim 14 , wherein the first electrode is positioned on the plurality of nano structures, the nano structures comprising a plurality of nano rods, and a portion of the first semiconductor layer where the plurality of the nano rods is not formed.

16. The element of claim 1 , wherein the support is positioned on an entire area of the metal layer of the second electrode.

17. The element of claim 1 , wherein the support is positioned on a portion of the metal layer of the second electrode.

18. The element of claim 1 , wherein the first electrode is configured to supply holes and electrons to the active layer.

19. The element of claim 1 , wherein the second electrode is configured to supply holes and electrons to the active layer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2025
From: LG ELECTRONICS INC.
To: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
Reel/Frame 072529/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2021
From: LG INNOTEK CO., LTD.
To: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
Reel/Frame 056366/0335 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2007
From: KIM, JONG WOOK; CHO, HYUN KYONG
To: LG ELECTRONICS INC.; LG INNOTEK CO., LTD.
Reel/Frame 019045/0425 →
Priority Claims (1)
KR 10-2005-0123861 · Dec 15, 2005 · national
Continuity (1)
Related Publication 20070166862A1 · Jul 19, 2007