Semiconductor devices with strained source/drain structures
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.
1. A device, comprising:
a semiconductor substrate;
a gate structure over the semiconductor substrate;
spacers overlying opposite sidewalls of the gate structure;
lightly doped source/drain (LDD) regions in the semiconductor substrate, interposed by the gate structure;
source/drain (S/D) regions in the semiconductor substrate, adjacent to the LDD regions and partially under the spacers, wherein each of the S/D regions comprises:
a first portion adjacent to a top surface of the semiconductor substrate;
a second portion surrounding the first portion; and
a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions; and
contact features over the S/D regions, wherein
the first, second, and third portions are formed in a trench of the semiconductor substrate,
the trench comprises:
a first sidewall section extending obliquely downward from the top surface of the semiconductor substrate and away from a center of the trench,
a second sidewall section further extending obliquely downward from the first sidewall section and toward the center of the trench, and
a bottom connected to the second sidewall section, and
the third portion includes:
an upper part included in a tip portion of the trench, the tip portion defined by the first and second sidewall sections, and
a lower part on the bottom of the trench, the lower part physically discontinuous from the upper part.
2. The device of claim 1 , wherein the upper part of the third portion is partially under the gate structure.
3. The device of claim 1 , wherein the first, second, and third portions contain Ge with a first atomic ratio, a second atomic ratio, and a third atomic ratio, the second ratio being less than the first and third ratios.
4. The device of claim 1 , wherein the first and third portions define strained features and the second portion defines a buffer layer.
5. The device of claim 1 , wherein the first, second, and third portions are doped epitaxial (epi) layers including a dopant selected from the group consisting of BF 2 , boron, arsenic, and phosphorous.
6. The device of claim 1 , wherein the first portion has a top surface substantially co-planar with or higher than the top surface of the semiconductor substrate.
7. The device of claim 1 , wherein the second portion is silicon germanium (SiGe) with an atomic ratio of Ge equal to or less than about 25 at %.