Resistance change memory

1. A resistance change memory comprising:

resistance change elements arrayed with a first space in a first direction and with a second space wider than the first space in a second direction orthogonal to the first direction, each of the resistance change elements including a variable resistance layer, a first conductive layer on the variable resistance layer, and a first insulating layer covering a sidewall of at least the variable resistance layer;

second conductive layers disposed on sidewalls of the first insulating layer and the first conductive layer of resistance change elements respectively, each of the second conductive layers having a width greater than or equal to a half of the first space in the first direction and having a width less than a half of the second space in the second direction, the second conductive layers functioning as a first bit line extending in the first direction by connecting the resistance change elements arrayed in the first direction; a second insulating layer disposed on a sidewall of the first bit line, and not filling the second space; and

a third conductive layer functioning as a second bit line extending in the first direction by filling the second space.

2. The memory of claim 1 , further comprising:

contact plugs disposed with a constant pitch in the first direction in the second space,

wherein a width in the second direction of the second conductive layer has a value in which the second conductive layer is separated from the contact plugs, and the third conductive layer connects the contact plugs.

3. The memory of claim 2 , further comprising:

active areas disposed in an array manner, each extending in a direction oblique to the first and second directions; and FETs disposed in the active areas respectively,

wherein each of the FETs includes a gate electrode as a word line extending in the second direction, a first source/drain layer connected to one of the resistance change elements, and a second source/drain layer connected to one of the contact plugs.

4. The memory of claim 3 , further comprising:

a contact plug disposed between the first source/drain layer and one of the resistance change elements.

5. The memory of claim 1 ,

wherein, the space SP 1 between the resistance change elements in the first direction is F, the space SP 2 between the resistance change elements in the second direction is greater than 2F, and is equal to or less than 3F.

6. The memory of claim 1 ,

wherein a side surface in the second direction of the first bit line has a shape connected convex curves.

7. The memory of claim 1 ,

wherein a side surface in the second direction of the second bit line has a shape connected concave curves.

8. The memory of claim 1 ,

wherein an upper surface of the second bit line is located lower than an upper surface of the first conductive layer.

9. The memory of claim 1 ,

wherein each of the resistance change elements is a magnetoresistive element.

10. The memory of claim 1 ,

wherein the first conductive layer is a hard mask layer.

11. A method of manufacturing the memory of claim 1 , the method comprising:

patterning the variable resistance layer by using the first conductive layer as a mask;

forming the first insulating layer as a sidewall insulating layer on a sidewall of at least the variable resistance layer;

forming the first bit line with a self-alignment to the resistance change elements by forming the second conductive layer as a sidewall conductive layer on sidewalls of the first insulating layer and the first conductive layer;

forming the second insulating layer as a sidewall insulating layer on a sidewall of the second conductive layer; and

forming the second bit line with a self-alignment to the first bit line by filling the second space with the third conductive layer.

12. The method of claim 11 , further comprising:

forming contact plugs with a constant pitch in the first direction in the second space,

wherein a width in the second direction of the second conductive layer has a value in which the second conductive layer is separated from the contact plugs, and the third conductive layer connects the contact plugs.

13. The method of claim 12 , further comprising:

forming active areas disposed in an array manner, each extending in a direction oblique to the first and second directions; and forming FETs in the active areas respectively,

wherein each of the FETs includes a gate electrode as a word line extending in the second direction, a first source/drain layer connected to one of the resistance change elements, and a second source/drain layer connected to one of the contact plugs.

14. The method of claim 13 , further comprising:

forming a contact plug disposed between the first source/drain layer and one of the resistance change elements.

15. The method of claim 11 ,

wherein, the space SP 1 between the resistance change elements in the first direction is F, the space SP 2 between the resistance change elements in the second direction is greater than 2F, and is equal to or less than 3F.

16. The method of claim 11 ,

wherein a side surface in the second direction of the first bit line has a shape connected convex curves.

17. The method of claim 11 ,

wherein a side surface in the second direction of the second bit line has a shape connected concave curves.

18. The method of claim 11 ,

wherein an upper surface of the second bit line is located lower than an upper surface of the first conductive layer.

19. The method of claim 11 ,

wherein each of the resistance change elements is a magnetoresistive element.

20. The method of claim 11 ,

wherein the first conductive layer is a hard mask layer.