Metal-free integrated circuits comprising graphene and carbon nanotubes
View Patent ↗An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
1. An integrated circuit comprising:
a graphene layer disposed on a substrate, the graphene layer comprising a region of undoped graphene and a region of doped graphene adjacent the region of undoped graphene, the undoped graphene comprising a channel of a transistor, and the region of doped graphene comprising a contact of the transistor;
a gate of the transistor disposed over the channel, the gate comprising a first portion of a carbon nanotube film;
a dielectric layer located on top of the graphene layer and underneath the gate of the transistor, such that the first portion of the etched carbon nanotube film is isolated from the undoped graphene channel by the dielectric layer;
a via formed through the dielectric layer, and filled with a second portion of the carbon nanotube film; and
a top level interconnect formed on top of the dielectric layer and in contact with the via, the top level interconnect comprising a third portion of the carbon nanotube film.
2. The integrated circuit of claim 1 , wherein the dielectric layer comprises an oxide material.
3. The integrated circuit of claim 1 , wherein the graphene layer is between about 0.35 nanometers (nm) and about 7 nm thick.
4. The integrated circuit of claim 1 , further comprising a substrate located underneath the graphene layer, the substrate comprising an oxide material.
5. The integrated circuit of claim 1 , wherein the doped graphene comprises an organic molecule.
6. The integrated circuit of claim 5 , wherein the organic molecule comprises polyethylemneimine.
7. The integrated circuit of claim 5 , wherein the organic molecule comprises diazonium.