Semiconductor devices and methods of manufacturing the same
Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.
1. A semiconductor device comprising:
a gate pattern comprising a gate insulation layer and a gate electrode formed on a substrate;
a source/drain region formed at substantially opposite sides of the gate pattern;
a silicide layer formed on the source/drain region;
an insulation layer formed on the gate pattern and the source/drain region; and
a contact hole formed through the insulation layer and exposing a predetermined region of the silicide layer,
wherein the gate pattern and the source and drain regions have a step difference between a top portion of the gate pattern and a top portion of the source and drain regions of about 250 Å or less from the substrate,
wherein the gate pattern and the source/drain region have an aspect ratio of less than about 3:1, and
wherein the aspect ratio is a ratio of the step difference between the top portion of the gate pattern and the top portion of the source/drain region to a width of the source/drain region.
2. The semiconductor device of claim 1 , wherein the gate electrode is formed of a metal containing material.
3. The semiconductor device of claim 1 , wherein the source/drain region is formed by epitaxially growing a silicon germanium layer in a trench formed by etching a predetermined region of the substrate.
4. The semiconductor device of claim 3 , wherein the trench has a hexagonal profile.
5. The semiconductor device of claim 1 , wherein the insulation layer includes a first insulation layer formed on the gate pattern and the source/drain region and a second insulation layer formed on the first insulation layer, and the first insulation layer and the second insulation layer have different etch ratios.
6. The semiconductor device of claim 5 , wherein the first insulation layer is formed of SiN and wherein the second insulation layer is formed of silicon oxide.