Internal, processing-unit memory for general-purpose use

1. A graphics processing unit (GPU), comprising:

a first internal memory comprising a memory controller and memory cells;

an execution unit coupled to the first internal memory, wherein the execution unit and the first internal memory are on a same die; and

an interface configured to provide high bandwidth dedicated internal memory access to a second internal memory of an additional processing unit, and further configured to provide high bandwidth dedicated internal memory access to the first internal memory by the additional processing unit, the first internal memory being combinable with the second internal memory for general-purpose use by the additional processing unit.

2. The processing unit of claim 1 , wherein the additional processing unit comprises a CPU.

3. The processing unit of claim 1 , wherein the additional processing unit comprises a central processing unit (CPU) and the second internal memory is a cache memory.

4. The processing unit of claim 1 , wherein the first internal memory comprises a stacked dynamic random-access memory.

5. The processing unit of claim 1 , wherein the first internal memory comprises an embedded dynamic random-access memory.

6. The processing unit of claim 1 , wherein the interface is further configured to couple the first internal memory to a display device.

7. The processing unit of claim 1 , wherein the memory controller is configured to provide access to the memory cells.

8. The processing unit of claim 1 , wherein the memory controller is coupled to a second memory controller of the additional processing unit.

9. The processing unit of claim 8 , wherein the execution unit sends a request to the memory controller to retrieve data from the second internal memory.

10. The processing unit of claim 8 , wherein the execution unit provides data to the memory controller to store in the second internal memory.

11. The processing unit of claim 1 , wherein data in the second internal memory of the additional processing unit is accessed by the same mechanism as the first internal memory.

12. A computer-program product comprising a non-transitory computer-readable storage medium containing instructions that, when executed on a computing device, define a graphics-processing unit (GPU), wherein the GPU comprises:

a first internal memory comprising a memory controller and memory cells;

an execution unit coupled to the first internal memory, wherein the execution unit and the first internal memory are on a same die; and

an interface configured to provide high bandwidth dedicated internal memory access to a second internal memory of an additional processing unit, and further configured to provide high bandwidth dedicated internal memory access to the first internal memory by the additional processing unit, the first internal memory being combinable with the second internal memory for general-purpose use by the additional processing unit.

13. The computer-program product of claim 12 , wherein the additional processing unit comprises a GPU.

14. The computer-program product of claim 12 , wherein the additional processing unit comprises a central processing unit (CPU) and the second internal memory is a cache memory.

15. The computer-program product of claim 12 , wherein the first internal memory of the GPU comprises a stacked dynamic random-access memory.

16. The computer-program product of claim 12 , wherein the first internal memory of the GPU comprises an embedded dynamic random-access memory.

17. The computer-program product of claim 12 , wherein the GPU embodied in hardware description language software.

18. The computer-program product of claim 12 , wherein the GPU is embodied in one of Verilog hardware description language software, Verilog-A hardware description language software, and VHDL hardware description language software.

19. A system, comprising:

a first graphics-processing unit (GPU) comprising a first internal memory comprising a first memory controller and first memory cells, and a first execution unit coupled to the first internal memory, wherein the first execution unit and the first internal memory are on a first same die;

a second GPU comprising a second internal memory comprising a second memory controller and second memory cells, and a second execution unit coupled to the second internal memory, wherein the second execution unit and the second internal memory are on a second same die; and

an interface configured to provide high bandwidth dedicated internal memory access to the second internal memory by the first GPU, and further configured to provide high bandwidth dedicated internal memory access to the first internal memory by the second GPU, the first internal memory being combinable with the second internal memory for general-purpose use by the second GPU.

20. The system of claim 19 , wherein the first internal memory comprises a stacked dynamic random-access memory.

21. The system of claim 19 , wherein the first internal memory comprises an embedded dynamic random-access memory.

22. The system of claim 19 , wherein the interface is further configured to couple the first internal memory and the second internal memory to a display device.

23. The system of claim 19 , further comprising:

an external memory;

a central-processing unit (CPU) comprising a cache memory; and

a bus coupled between the external memory and the CPU.

24. The system of claim 23 , wherein the first GPU further comprises an additional interface configured to provide high bandwidth dedicated internal memory access to the cache memory of the CPU, and further to provide high bandwidth dedicated internal memory access to the first internal memory by the CPU.

25. The system of claim 23 , wherein the second GPU further comprises an additional interface configured to provide high bandwidth dedicated internal memory access to the cache memory of the CPU, and further to provide high bandwidth dedicated internal memory access to the second internal memory by the CPU.