Interposer system and method
A system and method for providing an interposer is provided. An embodiment comprises forming a first region and a second region on an interposer wafer with a scribe region between the first region and the second region. The first region and the second region are then connected to each other through circuitry located over the scribe region. In another embodiment, the first region and the second region may be separated from each other and then encapsulated together prior to the first region being connected to the second region.
1. A semiconductor device comprising:
an interposer having a first side and a second side, the interposer comprising:
a first region comprising first circuitry;
a second region comprising second circuitry; and
a third region between the first region and the second region, the third region being devoid of circuitry and extending from the first side to the second side, wherein the third region is devoid of active devices; and
a conductive path between the first region and the second region, the conductive path extending over the third region.
2. The semiconductor device of claim 1 , wherein the third region is a scribe region between the first region and the second region.
3. The semiconductor device of claim 1 , wherein the third region comprises an encapsulant.
4. The semiconductor device of claim 1 , wherein the conductive path is part of a first semiconductor die.
5. The semiconductor device of claim 4 , further comprising a second semiconductor die attached to the first region.
6. The semiconductor device of claim 1 , wherein the first circuitry and the second circuitry have different patterns.
7. The semiconductor device of claim 1 , wherein the first circuitry and the second circuitry are the same.
8. A semiconductor device comprising:
an interposer with a first region free from functional circuitry between a second region and a third region, wherein the first region is free from active devices;
a first contact located in the second region;
a second contact located in the third region; and
a conductive path extending over the first region, the conductive path electrically connecting the first contact and the second contact.
9. The semiconductor device of claim 8 , wherein the conductive path is part of a first semiconductor die located over the first region.
10. The semiconductor device of claim 9 , further comprising a second semiconductor die located over the second region.
11. The semiconductor device of claim 8 , wherein the conductive path comprises a post-passivation interconnect located over the first region.
12. The semiconductor device of claim 11 , further comprising a first semiconductor die in contact with the post-passivation interconnect.
13. The semiconductor device of claim 8 , further comprising a seal ring located between the second region and the first region.
14. The semiconductor device of claim 8 , further comprising through substrate vias extending through the second region.
15. A semiconductor device comprising:
an interposer with a scribe region between a first region and a second region, wherein the first region comprises first circuitry and the second region comprises second circuitry;
a conductive path extending to electrically connect the first circuitry to the second circuitry, wherein the conductive path remains outside of the scribe region.
16. The semiconductor device of claim 15 , further comprising a first semiconductor die attached to a first surface of the interposer.
17. The semiconductor device of claim 16 , wherein the conductive path is at least partially located within the first semiconductor die.
18. The semiconductor device of claim 17 , further comprising a second semiconductor die attached to the first surface of the interposer.
19. The semiconductor device of claim 15 , wherein the first circuitry has a first pattern and the second circuitry has the first pattern.
20. The semiconductor device of claim 15 , wherein the first circuitry has a first pattern and the second circuitry has a second pattern different from the first pattern.