IP Library › Granted Patent US 8,810,268
Granted Patent B2
US 8,810,268 · App. 12/764,346 · Granted Aug 19, 2014

Built-in self-test circuit for liquid crystal display source driver

Inventors: Jui-Cheng Huang (Hsinchu, TW); Yung-Chow Peng (Hsinchu, TW); Ruey-Bin Sheen (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 8,810,268
App. No.
12/764,346
Granted
Aug 19, 2014
Kind
B2
Abstract

A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver includes at least one digital-to-analog converter (DAC) and at least one buffer coupled to the respective DAC, wherein the buffer is reconfigurable as a comparator. A first input signal and a second input signal are coupled to the comparator. The first input signal is a predetermined reference voltage level. The second input signal is a test offset voltage in a test range.

Claims (33)

1. A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver, comprising:

a plurality of digital-to-analog converters (DACs);

a plurality of buffers, wherein each buffer of the plurality of buffers is configured to be coupled to a respective DAC of the plurality of DACs and at least one buffer is reconfigurable as a comparator in response to a control signal, wherein the at least one buffer is configured to be disconnected from the DAC when the buffer is reconfigured as a comparator in a first test mode;

a first input signal node coupled to the comparator and configured to supply a first input signal that is a predetermined reference voltage level; and

a second input signal node coupled to the comparator and configured to supply a second input signal that is a test offset voltage in a test range.

2. The circuit of claim 1 , wherein the buffer comprises an operational amplifier (op-amp).

3. The circuit of claim 2 , wherein a feedback loop from an output of the op-amp to an inverting input of the op-amp is disconnected when the buffer is reconfigured as a comparator.

4. The circuit of claim 2 , wherein the first input signal node is coupled to a non-inverting input of the op-amp.

5. The circuit of claim 2 , wherein the second input signal node is coupled to an inverting input of the op-amp.

6. The circuit of claim 1 , wherein the test range is chosen for an offset voltage of an op-amp in the buffer.

7. The circuit of claim 1 , wherein the first input signal is supplied by the DAC.

8. The circuit of claim 1 , wherein the test range is chosen for a combined voltage of an offset voltage of an op-amp in the buffer and an output error of the DAC.

9. The circuit of claim 1 , wherein the test offset voltage is changed between a minimum value and a maximum value in the test range at a fixed voltage step.

10. A method for using a built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver, comprising:

reconfiguring at least one buffer as a comparator using a switching element to change at least one input of the comparator in response to a control signal, wherein each buffer of the at least one buffer is configured to be coupled to a respective digital-to-analog converter (DAC) of at least one DAC, wherein the at least one buffer is configured to be disconnected from the DAC when the buffer is reconfigured as a comparator in a first test mode;

supplying a first input signal to the comparator, wherein the first input signal is a predetermined reference voltage level;

supplying a second input signal to the comparator, wherein the second input signal is a test offset voltage in a test range; and

comparing the first input signal and the second input signal by the comparator to supply an output voltage.

11. The method of claim 10 , further comprising determining whether the output voltage is within a pass voltage range or a fail voltage range.

12. The method of claim 10 , wherein reconfiguring at least one buffer comprises disconnecting a feedback loop from an output of an op-amp in the buffer to an inverting input of the op-amp when the buffer is reconfigured as a comparator.

13. The method of claim 10 , further comprising choosing the test range for an offset voltage of an op-amp in the buffer.

14. The method of claim 10 , wherein the first input signal is supplied by the DAC.

15. The method of claim 10 , further comprising choosing the test range for a combined voltage of an offset voltage of an op-amp in the buffer and an output error of the DAC.

16. The method of claim 10 , further comprising changing the test offset voltage between a minimum value and a maximum value in the test range at a fixed voltage step.

17. A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver, comprising:

at least one digital-to-analog converter (DAC);

at least one buffer, wherein each buffer of the at least one buffer is configured to be coupled to a respective DAC of the at least one DAC and the buffer is reconfigurable as a comparator, wherein the at least one reconfigurable buffer includes at least one switching element configured to change at least one input of the at least one reconfigurable buffer in response to a control signal, and the at least one buffer is configured to be disconnected from the DAC when the buffer is reconfigured as a comparator in a first test mode;

a first input signal node coupled to the comparator and configured to supply a first input signal that is a predetermined reference voltage level; and

a second input signal node coupled to the comparator and configured to supply a second input signal that is a test offset voltage in a test range,

wherein the at least one reconfigurable buffer comprises an operational amplifier (op-amp), a feedback loop to an inverting input of the op-amp is disconnected when the buffer is reconfigured as a comparator, the first input signal node is coupled to a non-inverting input of the op-amp, and the second input signal node is coupled to an inverting input of the op-amp.

18. The circuit of claim 1 , wherein the at least one buffer is configured to be connected to the DAC when the buffer is reconfigured as a comparator in a second test mode.

19. The method of claim 10 , wherein the at least one buffer is configured to be connected to the DAC when the buffer is reconfigured as a comparator in a second test mode.

20. The circuit of claim 17 , wherein the at least one buffer is configured to be connected to the DAC when the buffer is reconfigured as a comparator in a second test mode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2010
From: HUANG, JUI-CHENG; PENG, YUNG-CHOW; SHEEN, RUEY-BIN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024265/0485 →
Continuity (1)
Related Publication 20110260746A1 · Oct 27, 2011