Semiconductor memory device including multilayer wiring layer
View Patent ↗The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.
1. A semiconductor memory device comprising:
a driver circuit comprising part of a single crystal semiconductor substrate;
a multilayer wiring layer overlapping the driver circuit, and the multilayer wiring layer comprising a wiring; and
a memory cell array layer overlapping the multilayer wiring layer, and the memory cell array layer comprising a memory cell,
wherein the memory cell is electrically connected to the driver circuit through the wiring,
wherein the memory cell comprises a transistor and a capacitor, and an electrode of the capacitor is electrically connected to one of a source and a drain of the transistor,
wherein the wiring includes copper or a copper alloy, and
wherein a channel region of the transistor is included in an oxide semiconductor layer.
2. The semiconductor memory device according to claim 1 , wherein the other of the source and the drain of the transistor is electrically connected to the driver circuit through the wiring.
3. The semiconductor memory device according to claim 1 , wherein the capacitor is a stack capacitor.
4. The semiconductor memory device according to claim 1 , wherein the single crystal semiconductor substrate is a single crystal silicon substrate.
5. A semiconductor memory device comprising:
a driver circuit comprising part of a single crystal semiconductor substrate;
a multilayer wiring layer overlapping the driver circuit, and the multilayer wiring layer comprising a wiring; and
a memory cell array layer overlapping the multilayer wiring layer, and the memory cell array layer comprising a memory cell,
wherein the memory cell is electrically connected to the driver circuit through the wiring,
wherein the memory cell comprises a transistor and a capacitor, and an electrode of the capacitor is electrically connected to one of a source and a drain of the transistor,
wherein the wiring includes copper or a copper alloy,
wherein a channel region of the transistor is included in an oxide semiconductor layer, and
wherein the capacitor overlaps the transistor.
6. The semiconductor memory device according to claim 5 , wherein the other of the source and the drain of the transistor is electrically connected to the driver circuit through the wiring.
7. The semiconductor memory device according to claim 5 , wherein the capacitor is a stack capacitor.
8. The semiconductor memory device according to claim 5 , wherein the single crystal semiconductor substrate is a single crystal silicon substrate.
9. A semiconductor memory device comprising:
a driver circuit;
a multilayer wiring layer overlapping the driver circuit, and the multilayer wiring layer comprising a wiring; and
a memory cell array layer overlapping the multilayer wiring layer, and the memory cell array layer comprising a memory cell,
wherein the memory cell is electrically connected to the driver circuit through the wiring,
wherein the memory cell comprises a transistor and a capacitor, and an electrode of the capacitor is electrically connected to one of a source and a drain of the transistor,
wherein the wiring includes copper or a copper alloy, and
wherein a channel region of the transistor is included in an oxide semiconductor layer.
10. The semiconductor memory device according to claim 9 , wherein the other of the source and the drain of the transistor is electrically connected to the driver circuit through the wiring.
11. The semiconductor memory device according to claim 9 , wherein the capacitor is a stack capacitor.
12. A semiconductor memory device comprising:
a driver circuit;
a multilayer wiring layer overlapping the driver circuit, and the multilayer wiring layer comprising a wiring; and
a memory cell array layer overlapping the multilayer wiring layer, and the memory cell array layer comprising a memory cell,
wherein the memory cell is electrically connected to the driver circuit through the wiring,
wherein the memory cell comprises a transistor and a capacitor, and an electrode of the capacitor is electrically connected to one of a source and a drain of the transistor,
wherein the wiring includes copper or a copper alloy,
wherein a channel region of the transistor is included in an oxide semiconductor layer, and
wherein the capacitor overlaps the transistor.
13. The semiconductor memory device according to claim 12 , wherein the other of the source and the drain of the transistor is electrically connected to the driver circuit through the wiring.
14. The semiconductor memory device according to claim 12 , wherein the capacitor is a stack capacitor.
15. The semiconductor memory device according to claim 1 , wherein the wiring is embedded in an insulating layer included in the multilayer wiring layer.
16. The semiconductor memory device according to claim 5 , wherein the wiring is embedded in an insulating layer included in the multilayer wiring layer.
17. The semiconductor memory device according to claim 9 , wherein the wiring is embedded in an insulating layer included in the multilayer wiring layer.
18. The semiconductor memory device according to claim 12 , wherein the wiring is embedded in an insulating layer included in the multilayer wiring layer.