Flash memory system and word line interleaving method thereof

1. A method of operating a memory having a memory cell array, memory cells in the memory cell array having varying cell conditions, and a plurality of wordlines coupled to memory cells along one direction of the array, the method comprising:

interleaving data for at least two different wordlines, interleaved data has a bit error rate equal to an average of the bit error rate of the at least two wordlines; and

programming data, including the interleaved data, to the memory cell array.

2. The method as claimed in claim 1 , further comprising, before interleaving data, ECC encoding data.

3. The method as claimed in claim 1 , wherein interleaving data for at least two different wordlines includes interleaving data for all wordlines of the memory cell array.

4. The method as claimed in claim 1 , wherein the memory cell array includes a plurality of memory blocks, the plurality of memory blocks including a plurality of planes connected by word lines and separated by selection lines.

5. The method as claimed in claim 4 , wherein interleaving data from at least two different wordlines includes interleaving data for different wordlines of a same plane.

6. The method as claimed in claim 4 , wherein interleaving data from at least two different wordlines includes interleaving data for all wordlines of a same plane.

7. The method as claimed in claim 4 , wherein interleaving data from at least two different wordlines includes interleaving data for a same wordline in different planes.

8. The method as claimed in claim 4 , wherein interleaving data for at least two different wordlines includes interleaving data for different wordlines within a plane across different planes.

9. The method as claimed in claim 1 , wherein each memory cell is a stacked memory cell, a width of a stacked memory cell increasing along a stacking direction of the plurality of memory cells, and wherein each wordline is coupled to memory cells along a direction orthogonal to the stacking direction.

10. The method as claimed in claim 1 , further comprising determining a size of word line data to be interleaved.

11. The method as claimed in claim 1 , wherein the memory cell array is a three-dimensional array.

12. The method as claimed in claim 1 , wherein the memory cell array is a flash memory cell array.

13. A memory system, comprising:

a memory device including

a memory cell array having an array of memory cells, and

a plurality of wordlines, each wordline being coupled to memory cells along a direction of the array;

a wordline interleaver configured to interleave data for at least two different wordlines, interleaved data has a bit error rate equal to an average of the bit error rate of the at least two wordlines; and

a memory controller configured to program data, including the interleaved data, to the memory cell array.

14. The memory system as claimed in claim 13 , wherein the wordline interleaver is part of the memory device.

15. The memory system as claimed in claim 13 , wherein the wordline interleaver is part of the memory controller.

16. The memory system as claimed in claim 13 , wherein the memory device and the memory controller are part of a storage device.

17. The memory system as claimed in claim 16 , wherein the wordline interleaver is part of the storage device.

18. The memory system as claimed in claim 17 , wherein the storage device is part of a memory card.

19. The memory system as claimed in claim 17 , wherein the storage device is part of a solid state device.

20. The memory system as claimed in claim 16 , further comprising a host to which the storage device is to communicate.

21. The memory system as claimed in claim 20 , wherein the wordline interleaver is in the host.

22. The memory system as claimed in claim 13 , wherein the wordline interleaver is configured to determine a size of word line data to be interleaved.

23. The memory system as claimed in claim 13 , wherein the memory cell array is a two-dimensional array.

24. The memory system as claimed in claim 13 , wherein the memory cell array is a three-dimensional array.

25. The memory system as claimed in claim 24 , wherein each memory cell is a stacked memory cell, a width of a stacked memory cell increasing along a stacking direction of the plurality of memory cells, and wherein each wordline is coupled to memory cells along a direction orthogonal to the stacking direction.

26. The memory system as claimed in claim 13 , further comprising an ECC decoder.

27. The memory system as claimed in claim 13 , wherein the wordline interleaver is configured to interleave data for all wordlines of the memory cell array.

28. The memory system as claimed in claim 13 , wherein the memory cell array includes a plurality of memory blocks, the plurality of memory blocks including a plurality of planes connected by word lines and separated by selection lines.

29. The memory system as claimed in claim 28 , wherein the wordline interleaver is configured to interleave data for different wordlines of a same plane.

30. The memory system as claimed in claim 28 , wherein the wordline interleaver is configured to interleave data for all wordlines of a same plane.

31. The memory system as claimed in claim 28 , wherein the wordline interleaver is configured to interleave data for a same wordline in different planes.

32. The memory system as claimed in claim 28 , wherein the wordline interleaver is configured to interleave data for different wordlines within a plane across different planes.

33. The memory system as claimed in claim 13 , wherein the memory cell array is a flash memory cell array.

34. An electronic device including the memory system recited in claim 13 .